View AD9739A_3112333.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

14-bit, 2.5 gsps, rf digital-to-analog converter AD9739A rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features direct rf synthesis at 2.5 gsps update rate dc to 1.25 ghz in baseband mode 1.25 ghz to 3.0 ghz in mix mode industry leading single/multicarrier if or rf synthesis dual-port lvds data interface up to 1.25 gsps operation source synchronous ddr clocking pin-compatible with the ad9739 programmable output current: 8.7 ma to 31.7 ma low power: 1.1 w at 2.5 gsps applications broadband communications systems docsis cmts systems military jammers instrumentation, automatic test equipment radar, avionics general description the AD9739A is a 14-bit, 2.5 gsps high performance rf dac capable of synthesizing wideband signals from dc up to 3 ghz. the AD9739A is pin and functionally compatible with the ad9739 with the exception that the AD9739A does not support synchronization and is specified to operate between 1.6 gsps and 2.5 gsps. by elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9739A between power-up cycles, thus allowing for possible system calibration. ac linearity and noise performance remain the same between the ad9739 and AD9739A. the inclusion of on-chip controllers simplifies system integ- ration. a dual-port, source synchronous, lvds interface simplifies the digital interface with existing fgpa/asic technology. on-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the dac core. a serial peripheral interface (spi) is used for device configuration as well as readback of status registers. the AD9739A is manufactured on a 0.18 m cmos process and operates from 1.8 v and 3.3 v supplies. it is supplied in a 160-ball chip scale ball grid array for reduced package parasitics. functional block diagram lvds ddr receiver dci sdo sdio s cl k cs dacclk dco db0[13:0] db1[13:0] clk distribution (div-by-4) data controller 4-to-1 data assembler spi reset dll (mu controller) lvds ddr receiver data latch ioutn ioutp vref i120 irq 1.2v dac bias AD9739A txdac core 09616-001 figure 1. product highlights 1. ability to synthesize high quality wideband signals with bandwidths of up to 1.25 ghz in the first or second nyquist zone. 2. a proprietary quad-switch dac architecture provides exceptional ac linearity performance while enabling mix- mode operation. 3. a dual-port, double data rate, lvds interface supports the maximum conversion rate of 2500 msps. 4. on-chip controllers manage external and internal clock domain skews. 5. programmable differential current output with a 8.66 ma to 31.66 ma range.
AD9739A rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? dc specifications ......................................................................... 3 ? lvds digital specifications ........................................................ 4 ? serial port specifications ............................................................. 5 ? ac specifications.......................................................................... 6 ? absolute maximum ratings............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution.................................................................................. 7 ? pin configurations and function descriptions ........................... 8 ? typical performance characteristics ........................................... 11 ? ac (normal mode).................................................................... 11 ? ac (mix mode) .......................................................................... 14 ? one-carrier docsis performance (normal mode) ............ 16 ? four-carrier docsis performance (normal mode) ........... 17 ? eight-carrier docsis performance (normal mode) .......... 18 ? 16-carrier docsis performance (normal mode) ............... 19 ? 32-carrier docsis performance (normal mode) ............... 20 ? 64- and 128-carrier docsis performance (normal mode)........................................................................... 21 ? terminology .................................................................................... 22 ? serial port interface (spi) register .............................................. 23 ? spi register map description .................................................. 23 ? spi operation ............................................................................. 23 ? spi register map ........................................................................ 25 ? theory of operation ...................................................................... 28 ? lvds data port interface.......................................................... 29 ? mu controller ............................................................................. 32 ? interrupt requests...................................................................... 33 ? analog interface considerations.................................................. 35 ? analog modes of operation ..................................................... 35 ? clock input considerations...................................................... 36 ? voltage reference ....................................................................... 37 ? analog outputs .......................................................................... 37 ? nonideal spectral artifacts....................................................... 39 ? lab evaluation of the AD9739A .............................................. 40 ? recommended start-up sequence .......................................... 41 ? outline dimensions ....................................................................... 43 ? ordering guide .......................................................................... 43 ? revision history 1/11revision 0: initial version
AD9739A rev. 0 | page 3 of 44 specifications dc specifications vdda = vdd33 = 3.3 v 6%, vddc = vdd = 1.8 v 6%, i outfs = 20 ma. table 1. parameter min typ max unit resolution 14 bits accuracy integral nonlinearity (inl) 2.5 lsb differential nonlinearity (dnl) 2.0 lsb analog outputs gain error (with internal reference) 5.5 % full-scale output current 8.66 20.2 31.66 ma output compliance range ?1.0 +1.0 v common-mode output resistance 10 m differential output resistance 70 output capacitance 1 pf dac clock input (dacclk_p, dacclk_n) differential peak-to-peak voltage 1.2 1.6 2.0 v common-mode voltage 900 mv clock rate 1.6 2.5 ghz temperature drift gain 60 ppm/c reference voltage 20 ppm/c reference internal reference voltage 1.15 1.2 1.25 v output resistance 5 k analog supply voltages vdda 3.1 3.3 3.5 v vddc 1.70 1.8 1.90 v digital supply voltages vdd33 3.10 3.3 3.5 v vdd 1.70 1.8 1.90 v supply currents and power dissipation, 2.0 gsps i vdda 37 38 ma i vddc 158 167 ma i vdd33 14.5 16 ma i vdd 173 183 ma power dissipation 0.770 w sleep mode, i vdda 2.5 2.75 ma power-down mode (all power-down bits set in register 0x01 and register 0x02) i vdda 0.02 ma i vddc 6 ma i vdd33 0.6 ma i vdd 0.1 ma supply currents and power dissipation, 2.5 gsps i vdda 37 ma i vddc 223 ma i vdd33 14.5 ma i vdd 215 ma power dissipation 0.960 w
AD9739A rev. 0 | page 4 of 44 lvds digital specifications vdda = vdd33 = 3.3 v 6%, vddc = vdd = 1.8 v 6%, i outfs = 20 ma. lvds drivers and receivers are compliant to the ieee standard 1596.3-1996 reduced range link, unless otherwise noted. table 2. parameter min typ max unit lvds data inputs (db0[13:0], db1[13:0]) 1 input common-mode voltage range, v com 825 1575 mv logic high differential input threshold, v ih_dth 175 400 mv logic low differential input threshold, v il_dth ?175 ?400 mv receiver differential input impedance, r in 80 120 input capacitance 1.2 pf lvds input rate 1250 msps lvds minimum data valid period (t mde ) (see figure 76 ) 344 ps lvds clock input (dci) 2 input common-mode voltage range, v com 825 1575 mv logic high differential input threshold, v ih_dth 175 400 mv logic low differential input threshold, v il_dth ?175 ?400 mv receiver differential input impedance, r in 80 120 input capacitance 1.2 pf maximum clock rate 625 mhz lvds clock output (dco) 3 output voltage high (dco_p or dco_n) 1375 mv output voltage low (dco_p or dco_n) 1025 mv output differential voltage, |v od | 150 200 250 mv output offset voltage, v os 1150 1250 mv output impedance, single-ended, r o 80 100 120 r o single-ended mismatch 10 % maximum clock rate 625 mhz 1 db0[x]p, db0[x]n, db1[x]p, and db1[x]n pins. 2 dci_p and dci_n pins. 3 dco_p and dco_n pins with 100 differential termination.
AD9739A rev. 0 | page 5 of 44 serial port specifications vdda = vdd33 = 3.3 v 6%, vddc = vdd = 1.8 v 6%. table 3 . parameter min typ max unit write operation (see figure 71 ) sclk clock rate, f sclk , 1/t sclk 20 mhz sclk clock high, t hi 18 ns sclk clock low, t low 18 ns sdio to sclk setup time, t ds 2 ns sclk to sdio hold time, t dh 1 ns cs to sclk setup time, t s 3 ns sclk to cs hold time, t h 2 ns read operation (see figure 72 and figure 73 ) sclk clock rate, f sclk , 1/t sclk 20 mhz sclk clock high, t hi 18 ns sclk clock low, t low 18 ns sdio to sclk setup time, t ds 2 ns sclk to sdio hold time, t dh 1 ns cs to sclk setup time, t s 3 ns sclk to sdio (or sdo) data valid time, t dv 15 ns cs to sdio (or sdo) output valid to high-z, t ez 2 ns inputs (sdi, sdio, sclk, cs ) voltage in high, v ih 2.0 3.3 v voltage in low, v il 0 0.8 v current in high, i ih ?10 +10 a current in low, i il ?10 +10 a output (sdio) voltage out high, v oh 2.4 3.5 v voltage out low, v ol 0 0.4 v current out high, i oh 4 ma current out low, i ol 4 ma
AD9739A rev. 0 | page 6 of 44 ac specifications vdda = vdd33 = 3.3 v 6%, vddc = vdd = 1.8 v 6%, i outfs = 20 ma. table 4. parameter min typ max unit dynamic performance maximum update rate (dacclk input) 800 2500 msps output settling time to 0.1% 13 ns spurious-free dynamic range (sfdr) f out = 100 mhz 69.5 dbc f out = 350 mhz 58.5 dbc f out = 550 mhz 54 dbc f out = 950 mhz 60 dbc two-tone intermodulation distortion (imd), f out2 = f out1 + 1.25 mhz f out = 100 mhz 94 dbc f out = 350 mhz 78 dbc f out = 550 mhz 72 dbc f out = 950 mhz 68 dbc noise spectral density (nsd), 0 dbfs single tone f out = 100 mhz ?166 dbm/hz f out = 350 mhz ?161 dbm/hz f out = 550 mhz ?160 dbm/hz f out = 850 mhz ?160 dbm/hz wcdma aclr (single carrier), adjacent/alternate adjacent channel f dac = 2457.6 msps f out = 350 mhz 80/80 dbc f dac = 2457.6 msps, f out = 950 mhz 78/79 dbc f dac = 2457.6 msps, f out = 1700 mhz (mix mode) 74/74 dbc f dac = 2457.6 msps, f out = 2100 mhz (mix mode) 69/72 dbc
AD9739A rev. 0 | page 7 of 44 absolute maximum ratings table 5. parameter with respect to rating vdda vssa ?0.3 v to +3.6 v vdd33 vss ?0.3 v to +3.6 v vdd vss ?0.3 v to +1.98 v vddc vssc ?0.3 v to +1.98 v vssa vss ?0.3 v to +0.3 v vssa vssc ?0.3 v to +0.3 v vss vssc ?0.3 v to +0.3 v dacclk_p, dacclk_n vssc ?0.3 v to vddc + 0.18 v dci, dco vss ?0.3 v to vdd33 + 0.3 v lvds data inputs vss ?0.3 v to vdd33 + 0.3 v ioutp, ioutn vssa ?1.0 v to vdda + 0.3 v i120, vref vssa ?0.3 v to vdda + 0.3 v irq, cs , sclk, sdo, sdio, reset vss ?0.3 v to vdd33 + 0.3 v junction temperature 150c storage temperature ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 6. thermal resistance package type ja jc unit 160-ball csp_bga 31.2 7.0 c/w 1 1 with no airflow movement. esd caution
AD9739A rev. 0 | page 8 of 44 pin configurations and function descriptions a b c d e f g h j k l m n p 141312 11 10 876 32 19 54 vssa, analog supply ground vssa shield, analog supply ground shield vdda, 3.3v, analog supply 09616-002 figure 2. analog supply pins (top view) a b c d e f g h j k l m n p 141312 11 10 876 32 19 54 vss digital supply ground vdd33, 3.3v digital supply vdd, 1.8v, digital supply 09616-003 figure 3. digital supply pins (top view) a b c d e f g h j k l m n p 14 13 12 11 10 876 32 19 54 vssc, clock supply ground vddc, 1.8v, clock supply 09616-004 figure 4. digital lvds clock supply pins (top view) a b c d e f g h j k l m db1[0:13] p db1[0:13]n db0[0:13] p db0[0:13]n differential input signal (clock or data) dacclk_n dacclk_p n p 141312 11 10 876 32 19 54 dci_p/_n dco_p/_n 09616-005 figure 5. digital lvds input, clock i/o (top view)
AD9739A rev. 0 | page 9 of 44 a b c d e f g h j k l m n p 141312 11 10 876 32 19 54 irq cs sclk reset sdio sdo ioutn ioutp i120 vref 09616-006 figure 6. analog i/o and spi control pins (top view) table 7 . AD9739A pin function descriptions pin no. mnemonic description c1, c2, d1, d2, e1, e2, e3, e4 vddc 1.8 v clock supply input. a1, a2, a3, a4, a5, b1, b2, b3, b4, b5, c4, c5, d4, d5 vssc clock supply return. a10, a11, b10, b11, c10, c11, d10, d 11 vdda 3.3 v analog supply input. a12, a13, b12, b13, c12, c13, d12, d13, vssa analog supply return. a6, a9, b6, b9, c6, c9, d6, d9, f1, f2, f3, f4, e11, e12, e13, e14, f11, f12 vssa shield analog supply return shield. tie to vssa at the dac. a14 nc do not connect to this pin. a7, b7, c7, d7 ioutn dac negative current output source. a8, b8, c8, d8 ioutp dac positive current output source. b14 i120 nominal 1.2 v reference. tie to analog ground via a 10 k resistor to generate a 120 a reference current. c14 vref voltage reference input/output. decouple to vssa with a 1 nf capacitor. d14 nc factory test pin. do not connect to this pin. c3, d3 dacclk_n/dacclk_p negative/positive dac clock input (dacclk). f13 irq interrupt request open drain output. active high. pull up to vdd33 with a 10 k resistor. f14 reset reset input. active high. tie to vss if unused. g13 cs serial port enable input. g14 sdio serial port data input/output. h13 sclk serial port clock input. h14 sdo serial port data output. j3, j4, j11, j12 vdd33 3.3 v digital supply input. g1, g2, g3, g4, g11, g12 vdd 1.8 v digital supply. input. h1, h2, h3, h4, h11, h12, k3, k4, k11, k12 vss digital supply return. j1, j2 nc differential resistor of 200 ex ists between j1 and j2. do not connect to this pin. k1, k2 nc differential resistor of 100 ex ists between j1 and j2. do not connect to this pin. j13, j14 dco_p/dco_n positive/negative data clock output (dco). k13, k14 dci_p/dci_n positive/negative data clock input (dci). l1, m1 db1[0]p/db1[0]n port 1 posi tive/negative data input bit 0. l2, m2 db1[1]p/db1[1]n port 1 posi tive/negative data input bit 1. l3, m3 db1[2]p/db1[2]n port 1 posi tive/negative data input bit 2. l4, m4 db1[3]p/db1[3]n port 1 posi tive/negative data input bit 3.
AD9739A rev. 0 | page 10 of 44 pin no. mnemonic description l5, m5 db1[4]p/db1[4]n port 1 posi tive/negative data input bit 4. l6, m6 db1[5]p/db1[5]n port 1 posi tive/negative data input bit 5. l7, m7 db1[6]p/db1[6]n port 1 posi tive/negative data input bit 6. l8, m8 db1[7]p/db1[7]n port 1 posi tive/negative data input bit 7. l9, m9 db1[8]p/db1[8]n port 1 posi tive/negative data input bit 8. l10, m10 db1[9]p/db1[9]n port 1 posi tive/negative data input bit 9. l11, m11 db1[10]p/db1[10]n port 1 positive/negative data input bit 10. l12, m12 db1[11]p/db1[11]n port 1 positive/negative data input bit 11. l13, m13 db1[12]p/db1[12]n port 1 positive/negative data input bit 12. l14, m14 db1[13]p/db1[13]n port 1 positive/negative data input bit 13. n1, p1 db0[0]p/db0[0]n port 0 posi tive/negative data input bit 0. n2, p2 db0[1]p/db0[1]n port 0 posi tive/negative data input bit 1. n3, p3 db0[2]p/db0[2]n port 0 posi tive/negative data input bit 2. n4, p4 db0[3]p/db0[3]n port 0 posi tive/negative data input bit 3. n5, p5 db0[4]p/db0[4]n port 0 posi tive/negative data input bit 4. n6, p6 db0[5]p/db0[5]n port 0 posi tive/negative data input bit 5. n7, p7 db0[6]p/db0[6]n port 0 posi tive/negative data input bit 6. n8, p8 db0[7]p/db0[7]n port 0 posi tive/negative data input bit 7. n9, p9 db0[8]p/db0[8]n port 0 posi tive/negative data input bit 8. n10, p10 db0[9]p/db0[9]n port 0 posi tive/negative data input bit 9. n11, p11 db0[10]p/db0[10]n port 0 positive/negative data input bit 10. n12, p12 db0[11]p/db0[11]n port 0 positive/negative data input bit 11. n13, p13 db0[12]p/db0[12]n port 0 positive/negative data input bit 12. n14, p14 db0[13]p/db0[13]n port 0 positive/negative data input bit 13.
AD9739A rev. 0 | page 11 of 44 typical performance characteristics ac (normal mode) i outfs = 20 ma, nominal supplies, 25c, unless otherwise noted. vbw 10khz 10db/div stop 2.4ghz start 20mhz 09616-007 figure 7. single-tone spectrum at f out = 91 mhz, f dac = 2.4 gsps f out (mhz) sfdr (dbc) 30 35 40 45 50 55 60 65 70 75 80 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1.6gsps 1.2gsps 2.4gsps 2.0gsps 09616-008 figure 8. sfdr vs. f out over f dac nsd (dbm/hz) ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ? 150 1.2gsps 2.4gsps f out (mhz) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 09616-009 figure 9. single-tone nsd over f out vbw 10khz 10db/div stop 2.4ghz start 20mhz 09616-010 figure 10. single-tone spectrum at f out = 1091 mhz, f dac = 2.4 gsps f out (mhz) imd (dbc) 30 0 100 200 300 400 500 600 700 800 900 1000 35 40 45 50 55 60 65 70 75 80 85 90 95 100 1100 1200 1.2gsps 1.6gsps 2.0gsps 2.4gsps 09616-011 figure 11. imd vs. f out over f dac f out (mhz) nsd (dbm/hz) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 ?170 ?169 ?168 ?167 ?166 ?165 ?164 ?163 ?162 ?161 ? 160 2.4gsps 1.2gsps 09616-012 figure 12. eight-tone nsd over f out
AD9739A rev. 0 | page 12 of 44 f dac = 2 gsps, i outfs = 20 ma, nominal supplies, 25c, unless otherwise noted. ?3dbfs 0dbfs f out (mhz) sfdr (dbc) 30 40 50 60 70 80 90 0 100 200 300 400 500 600 700 800 900 1000 ?6dbfs 09616-013 figure 13. sfdr vs. f out over digital full scale f out (mhz) sfdr (db) 30 0 100 200 300 400 500 600 700 800 900 1000 40 50 60 70 80 90 0dbfs ?3dbfs ?6dbfs 09616-014 figure 14. sfdr for second harmonic over f out vs. digital full scale f out (mhz) sfdr (dbc) 30 40 50 60 70 80 90 0 100 200 300 400 500 600 700 800 900 1000 10ma fs 20ma fs 30ma fs 09616-015 figure 15. sfdr vs, f out over dac i outfs f out (mhz) imd (dbc) 30 40 50 60 70 80 90 100 110 0 100 200 300 400 500 600 700 800 900 1000 0dbfs ?6dbfs ?3dbfs 09616-016 figure 16. imd vs. f out over digital full scale f out (mhz) sfdr (db) 30 0 100 200 300 400 500 600 700 800 900 1000 40 50 60 70 80 90 ?6dbfs ?3dbfs 0dbfs 0 9616-017 figure 17. sfdr for third harmonic over f out vs. digital full scale f out (mhz) imd (dbc) 30 40 50 60 70 80 90 100 110 0 100 200 300 400 500 600 700 800 900 1000 10ma fs 20ma fs 30ma fs 09616-018 figure 18. imd vs. f out over dac i outfs
AD9739A rev. 0 | page 13 of 44 f out (mhz) sfdr (dbc) 30 40 50 60 70 80 90 0 100 200 300 400 500 600 700 800 900 1000 +25c +85c ?40c 09616-019 figure 19. sfdr vs. f out over temperature ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ? 150 0 200 400 600 800 1000 100 300 500 700 900 f out (mhz) nsd (dbm/hz) +25c ?40c +85c 09616-020 figure 20. single-tone nsd vs. f out over temperature vbw 300khz 10db/div span 53.84mhz sweep 174.6ms (601pts) center 350.27mhz #res bw 30khz rms results carrier power ?14.54dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 (dbc) ?79.90 ?80.60 ?80.90 ?80.62 ?80.76 (dbm) ?94.44 ?95.14 ?95.45 ?95.16 ?95.30 lower (dbc) ?79.03 ?79.36 ?80.73 ?80.97 ?80.95 (dbm) ?93.57 ?94.40 ?95.27 ?95.51 ?95.49 upper 09616-021 figure 21. single-carrier wcdma at 350 mhz, f dac = 2457.6 msps f out (mhz) imd (dbc) 30 40 50 60 70 80 90 100 110 0 100 200 300 400 500 600 700 800 900 1000 +25c ?40c +85c 09616-022 figure 22. imd vs. f out over temperature ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ? 150 0 200 400 600 800 1000 100 300 500 700 900 f out (mhz) nsd (dbm/hz) +25c ?40c +85c 09616-023 figure 23. eight-tone nsd vs. f out over temperature ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 0 122.88 245.76 368.64 491.52 614.40 737.28 860.16 983.04 1105.90 1228.80 first adj ch second adj ch fifth adj ch f out (mhz) aclr (dbc) 09616-108 figure 24. four-carrier wcdma at 350 mhz, f dac = 2457.6 msps
AD9739A rev. 0 | page 14 of 44 ac (mix mode) f dac = 2.4 gsps, i outfs = 20 ma, nominal supplies, 25c, unless otherwise noted. vbw 10khz 10db/div stop 2.4ghz sweep 28.7s (601pts) start 20mhz #res bw 10khz 09616-026 figure 25. single-tone spectrum at f out = 2.31 ghz, f dac = 2.4 gsps 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f out (mhz) sfdr (dbc) 09616-027 figure 26. sfdr in mix mode vs. f out at 2.4 gsps vbw 300khz 10db/div span 53.84mhz sweep 174.6ms (601pts) center 2.10706mhz #res vw 30khz rms results carrier power ?21.43dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 (dbc) ?68.99 ?72.09 ?72.86 ?74.34 ?74.77 (dbm) ?90.43 ?93.52 ?94.30 ?95.77 ?96.20 lower (dbc) ?63.94 ?71.07 ?71.34 ?72.60 ?73.26 (dbm) ?90.37 ?92.50 ?92.77 ?94.03 ?94.70 upper 09616-032 figure 27. typical single-carrier wc dma aclr performance at 2.1 ghz, f dac = 2457.6 msps (second nyquist zone) vbw 10khz 10db/div stop 2.4ghz start 20mhz stop 2.4ghz sweep 28.7s (601pts) start 20mhz #res bw 10khz 09616-030 figure 28. single-tone spectrum in mix mode at f out = 1.31 ghz, f dac = 2.4 gsps 30 35 40 45 50 55 60 65 70 75 80 85 90 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 f out (mhz) imd (dbc) 09616-031 figure 29. imd in mix mode vs. f out at 2.4 gsps ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ? 40 1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686 second nyquist zone third nyquist zone first adj ch second adj ch fifth adj ch f out (mhz) aclr (dbc) 09616-025 figure 30. single-carrier wcdma aclr vs. f out at 2457.6 msps
AD9739A rev. 0 | page 15 of 44 vbw 300khz 10db/div span 53.84mhz sweep 174.6ms (601pts) center 2.807ghz #res bw 30khz rms results carrier power ?24.4dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 (dbc) ?64.90 ?66.27 ?68.44 ?70.20 ?70.85 (dbm) ?89.30 ?90.67 ?92.84 ?94.60 ?95.25 lower (dbc) ?63.82 ?65.70 ?66.55 ?68.95 ?70.45 (dbm) ?88.22 ?90.10 ?90.95 ?93.35 ?94.85 upper 09616-033 figure 31. typical single-carrier wc dma aclr performance at 2.8 ghz, f dac = 2457.6 msps (third nyquist zone) vbw 300khz 10db/div span 63.84mhz sweep 207ms (601pts) center 2.09758ghz #res bw 30khz rms results carrier power ?25.53dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 30 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 3.84 (dbc) 0.22 ?66.68 ?68.01 ?68.61 ?68.87 ?69.21 (dbm) ?25.31 ?92.21 ?93.53 ?94.14 ?94.40 ?94.74 lower (dbc) 0.24 0.14 ?66.82 ?67.83 ?67.64 ?68.50 (dbm) ?25.29 ?25.38 ?92.35 ?93.36 ?93.17 ?94.03 upper 09616-034 figure 32. typical four-carrier wcdma aclr performance at 2.1 ghz, f dac = 2457.6 msps (second nyquist zone) vbw 300khz 10db/div span 63.84mhz sweep 207ms (601pts) center 2.81271ghz #res bw 30khz rms results carrier power ?27.98dbm/ 3.84mhz freq offset (mhz) 5 10 15 20 25 30 ref bw (mhz) 3.84 3.84 3.84 3.84 3.84 3.84 (dbc) ?0.42 ?64.32 ?66.03 ?66.27 ?66.82 ?67.16 (dbm) ?28.40 ?92.30 ?94.01 ?94.24 ?94.79 ?95.13 lower (dbc) ?0.10 ?0.08 ?65.37 ?66.06 ?63.36 ?66.54 (dbm) ?28.07 ?28.06 ?93.34 ?94.03 ?93.34 ?94.51 upper 09616-035 figure 33. typical four-carrier wcdma aclr performance at 2.8 ghz, f dac = 2457.6 msps (third nyquist zone)
AD9739A rev. 0 | page 16 of 44 one-carrier docsis performance (normal mode) f dac = 20 ma, f dac = 2.4576 gsps, nominal supplies, 25c, unless otherwise noted. 1 2 ? 1 4 ? 1 5 ? 1 3 ? 1 vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function value function width function ?11.475dbm ?77.042db ?76.238db ?74.526db ?75.919db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?11.476dbm ?77.042db ?76.238db ?74.526db ?75.919db f f f f f 1 1 1 1 1 1 2 3 4 5 x n ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 200mhz 199.60mhz 400.05mhz 597.65mhz 413.35mhz 09616-036 11db/div ?31 ?42 ?53 ?64 ?75 ?86 ?97 ?108 ?119 figure 34. low band wideband aclr vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?10.231dbm ?76.425db ?75.626db ?70.658db ?75.824db ?78.118db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?10.231dbm ?76.444db ?75.649db ?70.658db ?75.836db ?78.054db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 549.60mhz ?485.35mhz 127.40mhz 254.70mhz 63.75mhz 293.65mhz 09616-037 1 2 ? 1 4 ? 1 5 ? 1 6 ? 1 3 ? 1 11db/div ?31 ?42 ?53 ?64 ?75 ?86 ?97 ?108 ?119 figure 35. mid band wideband aclr 11db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function value function width function ?13.658dbm ?65.548db ?66.990db ?69.049db ?72.789db 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?13.703dbm ?65.548db ?66.990db ?69.044db ?72.789db f f f f f 1 1 1 1 1 1 2 3 4 5 x n ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 979.00mhz ?484.40mhz ?118.65mhz ?613.60mhz ?365.65mhz 09616-038 1 4 ? 1 3 ? 1 5 ? 1 2 ? 1 ?31 ?42 ?53 ?64 ?75 ?86 ?97 ?108 ?119 figure 36. high band wideband aclr span 54mhz sweep 1.49s vbw 3khz center 200mhz #res bw 30khz upper filter off off off off off dbc ?60.16 ?81.26 ?80.72 ?80.76 ?80.78 dbc ?59.38 ?81.23 ?80.71 ?80.72 ?80.73 dbm ?70.35 ?91.45 ?90.91 ?90.95 ?90.97 lower dbm ?69.57 ?91.42 ?90.90 ?90.91 ?90.92 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?10.190dbm/6mhz acp-ibw 10db/di v ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 ?80.7dbc ?80.7dbc ?80.7dbc ?81.2dbc ?10.2dbm ?81.3dbc ?80.7dbc ?80.8dbc ?80.8dbc 09616-039 figure 37. low band narrow-band aclr span 54mhz sweep 1.49s vbw 3khz center 550mhz #res bw 30khz upper filter off off off off off dbc ?58.53 ?74.41 ?75.55 ?76.69 ?77.67 dbm ?68.90 ?84.78 ?85.92 ?87.06 ?88.03 lower dbc ?57.91 ?75.09 ?76.29 ?77.63 ?78.51 dbm ?68.28 ?85.46 ?86.65 ?88.00 ?88.88 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?10.368dbm/6mhz acp-ibw 10db/di v ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 ?78.5dbc ?77.6dbc ?76.3dbc ?75.1dbc ?10.4dbm ?74.4dbc ?75.6dbc ?77.7dbc ?76.7dbc 09616-040 figure 38. mid band narrow-band aclr span 54mhz sweep 1.49s vbw 3khz center 980mhz #res bw 30khz upper filter off off off off off dbc ?59.15 ?67.94 ?68.58 ?70.64 ?72.35 dbm ?71.93 ?80.72 ?81.35 ?83.42 ?85.13 lower dbc ?60.38 ?68.67 ?69.90 ?71.12 ?72.61 dbm ?73.15 ?81.44 ?82.68 ?83.90 ?85.39 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?12.778dbm/6mhz acp-ibw ?72.6dbc ?71.1dbc ?69.9dbc ?68.7dbc ?12.6dbm ?67.9dbc ?68.6dbc ?70.6dbc ?72.3dbc 09616-041 10db/di v ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?115 figure 39. high band narrow-band aclr
AD9739A rev. 0 | page 17 of 44 four-carrier docsis performance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, 25c, unless otherwise noted. 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?18.064dbm ?72.097db ?72.882db ?72.292db ?76.776db ?71.133db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?18.065dbm ?72.097db ?72.882db ?72.292db ?76.776db ?71.133db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 217.50mhz 201.10mhz 417.70mhz 608.65mhz ?124.75mhz 395.85mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-042 figure 40. low band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?18.760dbm ?69.536db ?71.601db ?72.833db ?75.320db ?71.997db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?18.760dbm ?69.536db ?71.601db ?72.824db ?75.786db ?71.997db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 667.80mhz ?192.20mhz ?98.15mhz ?614.00mhz ?567.45mhz ?55.40mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-043 figure 41. mid band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function value function width function ?21.029dbm ?60.683db ?69.390db ?71.847db ?66.954db ?68.889db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?21.040dbm ?60.683db ?69.390db ?71.954db ?66.954db ?68.889db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 987.95mhz ?490.50mhz ?624.45mhz ?738.45mhz ?130.46mhz ?374.60mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-044 figure 42. high band wideband aclr span 54mhz sweep 1.49s vbw 3khz center 210mhz #res bw 30khz upper filter off off off off off dbc ?58.78 ?73.56 ?75.42 ?78.08 ?79.06 dbm ?76.34 ?91.12 ?92.98 ?95.64 ?96.62 lower dbc ?11.15 ?0.454 ?0.065 ?0.091 ?53.44 dbm ?28.70 ?18.01 ?17.62 ?17.65 ?70.99 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?17.556dbm/6mhz acp-ibw 10db/di v ?53.4dbc ?0.1dbc ?0.1dbc ?0.5dbc ?17.6dbm ?73.6dbc ?75.4dbc ?79.1dbc ?78.1dbc 09616-045 ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 figure 43. low band narrow-band aclr (worst side) span 54mhz sweep 1.49s vbw 3khz center 650mhz #res bw 30khz upper filter off off off off off dbc ?11.18 ?0.294 ?0.075 ?0.145 ?50.21 dbm ?30.68 ?19.80 ?19.58 ?19.65 ?69.71 lower dbc ?61.84 ?72.95 ?74.99 ?76.38 ?76.59 dbm ?81.35 ?92.45 ?94.49 ?95.89 ?96.10 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?19.503dbm/6mhz acp-ibw 10db/di v ?76.6dbc ?76.4dbc ?75.0dbc ?72.9dbc ?19.5dbm ?0.3dbc ?0.1dbc ?50.2dbc ?0.1dbc 09616-046 ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 figure 44. mid band narrow-band aclr (worst side) span 54mhz sweep 1.49s vbw 3khz center 970mhz #res bw 30khz upper filter off off off off off dbc ?10.77 ?0.522 ?0.140 ?0.511 ?52.31 dbm ?31.44 ?21.19 ?20.81 ?21.18 ?72.98 lower dbc ?60.65 ?68.68 ?70.67 ?72.96 ?74.22 dbm ?81.32 ?89.34 ?91.33 ?93.63 ?94.89 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?20.666dbm/6mhz acp-ibw 10db/di v ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 ?74.2dbc ?73.0dbc ?70.7dbc ?68.7dbc ?20.7dbm ?0.5dbc 0.1dbc ?52.3dbc ?0.5dbc 09616-047 figure 45. high band narrow-band aclr (worst side)
AD9739A rev. 0 | page 18 of 44 eight-carrier docsis performance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, 25c, unless otherwise noted. 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function value function width function ?23.279dbm ?67.448db ?72.764db ?68.258db ?69.581db ?66.457db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?23.278dbm ?67.453db ?72.684db ?68.278db ?69.581db ?66.474db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 241.25mhz 198.25mhz ?135.20mhz 746.40mhz 20.60mhz 371.15mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-048 figure 46. low band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?23.977dbm ?69.185db ?68.551db ?69.938db ?72.083db ?65.009db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?23.977dbm ?69.185db ?68.551db ?69.923db ?72.145db ?65.009db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 667.80mhz ?171.30mhz ?98.15mhz ?614.00mhz ?567.45mhz ?55.40mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-049 figure 47. mid band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?25.435dbm ?61.947db ?67.532db ?69.602db ?65.237db ?64.615db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?25.435dbm ?61.947db ?67.517db ?69.583db ?65.237db ?64.615db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 990.80mhz ?481.00mhz ?633.95mhz ?734.65mhz ?128.55mhz ?378.40mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-050 figure 48. high band wideband aclr span 54mhz sweep 1.49s vbw 3khz center 222mhz #res bw 30khz upper filter off off off off off dbc ?59.41 ?69.96 ?69.91 ?69.74 ?70.08 dbm ?81.28 ?91.83 ?91.78 ?91.62 ?91.95 lower dbc ?10.98 ?0.334 ?0.087 ?0.034 ?0.031 dbm ?32.85 ?22.21 ?21.79 ?21.91 ?21.84 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?21.874dbm/6mhz acp-ibw 10db/di v 0dbc 0dbc 0.1dbc ?0.3dbc ?21.9dbm ?70.0dbc ?69.9dbc ?70.1dbc ?69.7dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 09616-051 figure 49. low band narrow-band aclr (worst side) span 54mhz sweep 1.49s vbw 3khz center 622mhz #res bw 30khz upper filter off off off off off dbc ?61.38 ?69.17 ?68.64 ?69.33 ?69.18 dbc ?84.07 ?91.86 ?91.33 ?92.02 ?91.88 lower dbc ?11.01 ?0.339 ?0.135 ?0.089 ?0.049 dbc ?33.70 ?23.03 ?22.83 ?22.78 ?22.74 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?22.691dbm/6mhz acp-ibw 10db/di v 0dbc ?0.1dbc ?0.1dbc ?0.3dbc ?22.7dbm ?69.2dbc ?68.6dbc ?69.2dbc ?69.3dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 09616-052 figure 50. mid band narrow-band aclr (worst side) span 54mhz sweep 1.49s vbw 3khz center 950mhz #res bw 30khz upper filter off off off off off dbc ?10.93 ?0.487 ?0.205 ?0.047 0.016 dbm ?36.27 ?25.83 ?25.55 ?25.39 ?25.33 lower dbc ?60.39 ?67.44 ?67.29 ?67.65 ?67.65 dbm ?85.73 ?92.78 ?92.63 ?93.00 ?93.00 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?25.344dbm/6mhz acp-ibw 10db/di v ?67.7dbc ?67.7dbc ?67.3dbc ?67.4dbc ?25.3dbm ?0.5dbc ?0.2dbc 0dbc 0dbc ?37 ?47 ?57 ?67 ?77 ?87 ?97 ?107 ?117 09616-053 figure 51. high band narrow-band aclr (worst side)
AD9739A rev. 0 | page 19 of 44 16-carrier docsis performance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, 25c, unless otherwise noted. 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?26.335dbm ?66.838db ?70.312db ?65.928db ?66.973db ?64.451db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?25.335dbm ?66.838db ?70.421db ?65.880db ?67.033db ?64.481db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 289.70mhz 202.05mhz ?183.65mhz 697.95mhz 18.70mhz 322.70mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-054 figure 52. low band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function value function width function ?28.317dbm ?64.672db ?65.207db ?64.574db 6mhz 6mhz 6mhz 6mhz band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?28.317dbm ?64.672db ?65.202db ?64.574db f f f f 1 1 1 1 1 2 3 4 x n ? 1 ? 1 ? 1 mode mkr scl trc 690.60mhz ?141.85mhz ?623.50mhz 152.65mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 3 ? 1 1 2 ? 1 4 ? 1 09616-055 figure 53. mid band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function value function width function ?27.960dbm ?61.110db ?63.332db ?65.483db ?62.779db ?59.828db 6mhz 6mhz 6mhz 6mhz 6mhz 6mhz band power band power band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?27.971dbm ?61.110db ?63.327db ?65.509db ?62.779db ?59.828db f f f f f f 1 1 1 1 1 1 1 2 3 4 5 6 x n ? 1 ? 1 ? 1 ? 1 ? 1 mode mkr scl trc 989.85mhz ?422.10mhz ?922.75mhz ?668.15mhz ?137.10mhz ?377.45mhz ?38 ?48 ?58 ?68 ?78 ?88 ?98 ?108 ?118 5 ? 1 6 ? 1 3 ? 1 1 2 ? 1 4 ? 1 09616-056 figure 54. high band wideband aclr span 54mhz sweep 1.49s vbw 3khz center 200mhz #res bw 30khz upper filter off off off off off dbc ?11.03 ?0.368 0.137 0.010 0.035 dbm ?35.85 ?25.19 ?24.68 ?24.81 ?24.78 lower dbc ?60.64 ?68.49 ?67.43 ?67.32 ?67.44 dbm ?85.46 ?93.30 ?92.24 ?92.13 ?92.26 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?24.819dbm/6mhz acp-ibw 10db/di v ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?67.4dbc ?67.3dbc ?67.4dbc ?68.5dbc ?24.8dbm ?0.4dbc ?0.1dbc 0dbc 0dbc 09616-057 figure 55. low band narrow-band aclr (worst side) span 54mhz sweep 1.49s vbw 3khz center 600mhz #res bw 30khz upper filter off off off off off dbc ?10.38 ?0.494 0.098 0.180 0.021 dbm ?36.49 ?26.58 ?25.98 ?25.90 ?26.06 lower dbc ?61.77 ?67.40 ?67.09 ?66.80 ?66.67 dbm ?87.85 ?93.48 ?93.18 ?92.88 ?92.75 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?26.083dbm/6mhz acp-ibw 10db/di v ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?66.7dbc ?66.8dbc ?67.1dbc ?67.4dbc ?26.1dbm ?0.5dbc 0.1dbc 0dbc 0.2dbc 09616-058 figure 56. mid band narrow-band aclr(worst side) span 54mhz sweep 1.49s vbw 3khz center 900mhz #res bw 30khz upper filter off off off off off dbc ?11.30 ?0.490 ?0.119 ?0.016 0.153 dbm ?39.73 ?28.92 ?28.55 ?28.45 ?28.28 lower dbc ?57.24 ?65.03 ?64.64 ?64.80 ?64.86 dbm ?85.68 ?93.46 ?93.08 ?93.24 ?93.29 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?28.435dbm/6mhz acp-ibw 10db/di v ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?64.9dbc ?64.8dbc ?64.6dbc ?65.0dbc ?28.4dbm ?0.5dbc ?0.1dbc 0.2dbc 0dbc 09616-059 figure 57. high band narrow-band aclr (worst side)
AD9739A rev. 0 | page 20 of 44 32-carrier docsis performance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, 25c, unless otherwise noted. 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?29.645dbm ?64.167db ?59.423db ?62.750db 6mhz 6mhz 6mhz 6mhz band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?29.646dbm ?64.175db ?59.429db ?62.750db f f f f 1 1 1 1 1 2 3 4 x n ? 1 ? 1 ? 1 mode mkr scl trc 384.70mhz ?283.40mhz 227.70mhz 325.55mhz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 3 ? 1 1 2 ? 1 4 ? 1 09616-060 figure 58. low band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz function va l u e function width function ?30.335dbm ?63.112db ?63.860db ?62.151db 6mhz 6mhz 6mhz 6mhz band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?30.335dbm ?63.136db ?63.860db ?62.151db f f f f 1 1 1 1 1 2 3 4 x n ? 1 ? 1 ? 1 mode mkr scl trc 685.85mhz ?611.15mhz ?243.50mhz 162.15mhz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 3 ? 1 1 2 ? 1 4 ? 1 09616-061 figure 59. mid band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 function value function width function ?31.516dbm ?59.997db ?60.535db ?57.763db 6mhz 6mhz 6mhz 6mhz band power band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?31.616dbm ?59.997db ?60.458db ?57.761db f f f f 1 1 1 1 1 2 3 4 x n ? 1 ? 1 ? 1 mode mkr scl trc 985.10mhz ?334.70mhz ?909.45mhz ?373.65mhz 3 ? 1 1 2 ? 1 4 ? 1 09616-062 figure 60. high band wideband aclr span 54mhz sweep 1.49s vbw 3khz center 200mhz #res bw 30khz upper filter off off off off off dbc ?10.78 ?0.487 ?0.175 ?0.151 ?0.061 dbm ?40.09 ?29.80 ?29.49 ?29.46 ?29.37 lower dbc ?58.76 ?63.30 ?63.05 ?63.21 ?63.46 dbm ?88.07 ?92.61 ?92.36 ?92.52 ?92.78 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?29.311dbm/6mhz acp-ibw 10db/di v ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?63.5dbc ?63.2dbc ?63.1dbc ?63.3dbc ?29.3dbm ?0.5dbc ?0.2dbc ?0.1dbc ?0.2dbc 09616-063 figure 61. low band narrow-band aclr (worst side) span 54mhz sweep 1.49s vbw 3khz center 600mhz #res bw 30khz upper filter off off off off off dbc ?10.40 ?0.515 ?0.178 ?0.069 ?0.197 dbm ?39.65 ?29.77 ?29.43 ?29.32 ?29.45 lower dbc ?60.64 ?65.26 ?64.73 ?64.65 ?64.68 dbm ?89.90 ?94.52 ?93.99 ?93.91 ?93.93 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?29.255dbm/6mhz acp-ibw 10db/di v ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?64.7dbc ?64.7dbc ?64.7dbc ?65.3dbc ?29.3dbm ?0.5dbc ?0.1dbc ?0.2dbc ?0.1dbc 09616-064 figure 62. mid band narrow-band aclr(worst side) span 54mhz sweep 1.49s vbw 3khz center 800mhz #res bw 30khz upper filter off off off off off dbc ?10.84 ?0.437 ?0.354 ?0.455 ?0.410 dbm ?41.59 ?31.18 ?31.10 ?31.20 ?31.16 lower dbc ?60.75 ?63.18 ?62.76 ?62.74 ?62.84 dbm ?91.49 ?93.92 ?93.50 ?93.48 ?93.59 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?30.746dbm/6mhz acp-ibw 10db/di v ?44 ?54 ?64 ?74 ?84 ?94 ?104 ?114 ?124 ?62.8dbc ?62.7dbc ?62.8dbc ?0.4dbc ?30.7dbm ?0.4dbc ?0.4dbc ?0.5dbc ?63.2dbc 09616-065 figure 63. high band narrow-band aclr (worst side)
AD9739A rev. 0 | page 21 of 44 64- and 128-carrier docsis performance (normal mode) i outfs = 20 ma, f dac = 2.4576 gsps, nominal supplies, 25c, unless otherwise noted. 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 function value function width function ?33.209dbm ?58.804db ?55.165db 6mhz 6mhz 6mhz band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?33.210dbm ?58.746db ?55.165db f f f 1 1 1 1 2 3 x n ? 1 ? 1 mode mkr scl trc 478.75mhz 372.10mhz 132.70mhz 3 ? 1 2 ? 1 1 09616-066 figure 64. low band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 function va l u e function width function ?35.873dbm ?58.625db ?59.286db 6mhz 6mhz 6mhz band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?35.872dbm ?58.581db ?59.214db f f f 1 1 1 1 2 3 x n ? 1 ? 1 mode mkr scl trc 978.45mhz ?901.85mhz ?561.75mhz 3 ? 1 2 ? 1 1 09616-067 figure 65. mid band wideband aclr 10db/div vbw 2khz stop 1ghz sweep 24.1s (1001pts) start 50mhz #res bw 20khz ?52 ?62 ?72 ?82 ?92 ?102 ?112 ?122 ?132 function va l u e function width function ?37.983dbm ?55.764db ?56.953db 6mhz 6mhz 6mhz band power band power band power ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) y ?37.954dbm ?55.764db ?57.007db f f f 1 1 1 1 2 3 x n ? 1 ? 1 mode mkr scl trc 988.90mhz ?481.95mhz ?925.60mhz 1 2 ? 1 3 ? 1 09616-068 figure 66. 128-carrier high band wideband aclr span 54mhz sweep 1.49s vbw 3khz center 478mhz #res bw 30khz upper filter off off off off off dbc ?60.80 ?62.25 ?61.47 ?61.54 ?61.40 dbm ?93.21 ?94.66 ?93.88 ?93.95 ?93.81 lower dbc ?10.83 ?0.267 0.139 0.201 0.308 dbm ?43.24 ?32.68 ?32.27 ?32.21 ?32.10 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?32.409dbm/6mhz acp-ibw 10db/di v ?51 ?61 ?71 ?81 ?91 ?101 ?111 ?121 ?131 0.3dbc 0.2dbc 0.1dbc ?0.3dbc ?32.4dbm ?62.3dbc ?61.5dbc ?61.4dbc ?61.5dbc 09616-069 figure 67. low band narrow-band aclr (worst side) span 54mhz sweep 1.49s vbw 3khz center 600mhz #res bw 30khz upper filter off off off off off dbc ?11.84 ?0.284 ?0.099 ?0.221 ?0.060 dbm ?45.04 ?33.84 ?33.46 ?33.34 ?33.50 lower dbc ?60.02 ?61.11 ?60.57 ?60.64 ?60.58 dbm ?93.58 ?94.66 ?94.13 ?94.20 ?94.14 integ bw 750.0khz 5.250mhz 6.000mhz 6.000mhz 6.000mhz offset freq 3.375mhz 6.375mhz 12.00mhz 18.00mhz 24.00mhz carrier power ?33.558dbm/6mhz acp-ibw 10db/di v ?51 ?61 ?71 ?81 ?91 ?101 ?111 ?121 ?131 ?60.6dbc 33.6dbm 0.3dbc 0.1dbc 0.1dbc 0.2dbc ?60.6dbc ?61.1dbc ?60.6dbc 09616-070 figure 68. mid band narrow-band aclr(worst side)
AD9739A rev. 0 | page 22 of 44 terminology linearity error (integral nonlinearity or inl) the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale. differential nonlinearity (dnl) the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of 0 is called the offset error. for ioutp, 0 ma output is expected when the inputs are all 0s. for ioutn, 0 ma output is expected when all inputs are set to 1. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. spurious-free dynamic range the difference, in decibels (db), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). noise spectral density (nsd) nsd is the converter noise power per unit of bandwidth. this is usually specified in dbm/hz in the presence of a 0 dbm full- scale signal. adjacent channel leakage ratio (aclr) the adjacent channel leakage (power) ratio is a ratio, in dbc, of the measured power within a channel relative to its adjacent channels. modulation error ratio (mer) mo dulated signals create a discrete set of output values referred to as a constellation. each symbol creates an output signal corresponding to one point on the constellation. mer is a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. i ntermodulation distortion (imd) i md is the result of two or more signals at different frequencies mixing together. many products are created according to the formula, af1 bf2, where a and b are integer values.
AD9739A rev. 0 | page 23 of 44 serial port interface (spi) register spi register map description the AD9739A contains a set of programmable registers described in table 9 that are used to configure and monitor various internal parameters. note the following points when programming the AD9739A spi registers: ? registers pertaining to similar functions are grouped together and assigned adjacent addresses. ? bits that are undefined within a register should be assigned a 0 when writing to that register. ? registers that are undefined should not be written to. ? a hardware or software reset is recommended upon power-up to place spi registers in a known state. ? a spi initialization routine is required as part of the boot process. see table 12 for an example procedure. reset issuing a hardware or software reset places the AD9739A spi registers in a known state. all spi registers (excluding 0x00) are set to their default states as described in table 9 upon issuing a reset. after issuing a reset, the spi initialization process need only write to registers that are required for the boot process as well as any other register settings that must be modified, depending on the target application. although the AD9739A does feature an internal power-on-reset (por), it is still recommended that a software or hardware reset be implemented shortly after power-up. the internal reset signal is derived from a logical or operation from the internal por signal, the reset pin, and the software reset state. a software reset can be issued via the reset bit (register 0x00, bit 5) by toggling the bit high then low. note that, because the msb/lsb format may still be unknown upon initial power-up (that is, internal por is unsuccessful), it is also recommended that the bit settings for bits[7:5] be mirrored onto bits[2:0] for the instruction cycle that issues a software reset. a hardware reset can be issued from a host or external supervisory ic by applying a high pulse with a minimum width of 40 ns to the reset pin (that is, pin f14). reset should be tied to vss if unused. table 8. spi registers pertaining to spi options address (hex) bit description 7 enable 3-wire spi 6 enable spi lsb first 0x00 5 software reset spi operation the serial port of the AD9739A shown in figure 69 has a 3- or 4-wire spi capability, allowing read/write access to all registers that configure the devices internal parameters. it provides a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. the 3.3 v serial i/o is compatible with most synchronous transfer formats, including the motorola? spi and the intel? ssr protocols. sdo (pin h14) sdio (pin g14) sclk (pin h13) cs (pin g13) ad9739 spi port 09616-072 figure 69. AD9739A spi port the default 4-wire spi interface consists of a clock (sclk), serial port enable ( cs ), serial data input (sdio), and serial data output (sdo). the inputs to sclk, cs , and sdio contain a schmitt trigger with a nominal hysteresis of 0.4 v centered about vdd33/2. the maximum frequency for sclk is 20 mhz. the sdo pin is active only during the transmission of data and remains three-stated at any other time. a 3-wire spi interface can be enabled by setting the sdio_dir bit (register 0x00, bit 7). this causes the sdio pin to become bidirectional such that output data only appears on the sdio pin during a read operation. the sdo pin remains three-stated in a 3-wire spi interface. instruction header information msb lsb 17 16 15 14 13 12 11 10 r/ w a6 a5 a4 a3 a2 a1 a0 an 8-bit instruction header must accompany each read and write operation. the msb is a r/ w indicator bit with logic high indicating a read operation. the remaining seven bits specify the address bits to be accessed during the data transfer portion. the eight data bits immediately follow the instruction header for both read and write operations. for write operations, registers change immediately upon writing to the last bit of each transfer byte. cs can be raised after each sequence of eight bits (except the last byte) to stall the bus. the serial transfer resumes when cs is lowered. stalling on nonbyte boundaries resets the spi.
AD9739A rev. 0 | page 24 of 44 the AD9739A serial port can support both most significant bit (msb) first and least significant bit (lsb) first data formats. figure 70 illustrates how the serial port words are formed for the msb first and lsb first modes. the bit order is controlled by the sdio_dir bit (register 0x00, bit 7). the default value is 0, msb first. when the lsb first bit is set high, the serial port interprets both instruction and data bytes lsb first. sclk sdata sclk sdata r/w r/w a1 a3 a2 a4 n1 n1 n2 n2 a0 a3 a1 a2 a0 a4 d7 1 d0 1 d1 1 d6 n d7 n d6 1 d1 n d0 n data transfer cycle instruction cycle data transfer cycle instruction cycle 09616-073 cs cs figure 70. spi timing, msb first (upper) and lsb first (lower) figure 71 illustrates the timing requirements for a write operation to the spi port. after the serial port enable ( cs ) signal goes low, data (sdio) pertaining to the instruction header is read on the rising edges of the clock (sclk). to initiate a write operation, the read/not-write bit is set low. after the instruction header is read, the eight data bits pertaining to the specified register are shifted into the sdio pin on the rising edge of the next eight clock cycles. figure 72 illustrates the timing for a 3-wire read operation to the spi port. after cs goes low, data (sdio) pertaining to the instruction header is read on the rising edges of sclk. a read operation occurs if the read/not-write indicator is set high. after the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the sdio pin on the falling edges of the next eight clock cycles. figure 73 illustrates the timing for a 4-wire read operation to the spi port. the timing is similar to the 3-wire read operation with the exception that data appears at the sdo pin only, while the sdio pin remains at high impedance throughout the operation. the sdo pin is an active output only during the data transfer phase and remains three-stated at all other times. d7 d6 a0 d1 n1 n0 t s sclk sdio 1/ f sclk t low t hi t ds t dh r/w d0 t h 0 9616-074 cs figure 71. spi write operation timing d7 d6 a0 d1 n1 t s s cl k sdio 1/ f sclk t low t hi t ds t dh r/w d0 t ez a2 a1 t dv 09616-075 cs figure 72. spi 3-wire re ad operation timing a0 cs n1 t s sclk sdio 1/ f sclk t low t hi t ds t dh r/w t ez a2 a1 t dv d7 d6 d1 sdo d0 t ez 09616-076 figure 73. spi 4-wire read operation timing
AD9739A rev. 0 | page 25 of 44 spi register map table 9. address (hex) name bit r/w default setting comments spi port configuration and software reset sdio_dir 7 r/w 0 0 = 4-wire spi, 1 = 3-wire spi. lsb/msb 6 r/w 0 0 = msb first, 1 = lsb first. 0x00 reset 5 r/w 0 software reset is recommended before modification of other spi registers from the default setting. setting the bit to 1 caus es all registers (except 0x00) to be set to the default setting. setting the bit to 0 corresponds to the inactive state, allowing the user to modify registers from the default setting. power-down lvds interface and txdac lvds_drvr_pd 5 r/w 0 lvds_rcvr_pd4 4 r/w 0 clk_rcvr_pd 1 r/w 0 0x01 dac_bias_pd 0 r/w 0 power-down of the lvds drivers/receivers and txdac. 0 = enable, 1 = disable. controller clock disable clkgen_pd 3 r/w 0 internal clk distribution enable: 0 = enable, 1 = disable. rec_cnt_clk 1 r/w 1 0x02 mu_cnt_clk 0 r/w 1 lvds receiver and mu controller clock disable. 0 = disable, 1 = enable. interrupt request (irq) enable/status mu_lst_en 3 w 0 mu_lck_en 2 w 0 rcv_lst_en 1 w 0 0x03 rcv_lck_en 0 w 0 this register enables the mu and lvds rx controllers to update their corresponding irq status bits in register 0x04, which defines whether the controller is locked (lck) or unlocked (lst). 0 = disable (resets the status bit), 1 = enable. mu_lst_irq 3 r 0 mu_lck_irq 2 r 0 rcv_lst_irq 1 r 0 0x04 rcv_lck_irq 0 r 0 this register indicates the status of the controllers. for lck_iqr bits: 0 = lost locked, 1 = locked. for lst_iqr bits: 0 = not lost locked, 1 = unlocked. note that, if the controller irq is serv iced, the relevant bits in register 0x03 should be reset by writing 0, followed by another write of 1 to enable. txdac full-scale current setting (i outfs ) and sleep 0x06 fsc_1 [7:0] r/w 0x00 fsc_2 [1:0] r/w sets the txdac i outfs current between 8 ma and 31 ma (default = 20 ma). i outfs = 0.0226 fsc[9:0] + 8.58, where fsc = 0 to 1023. 0x07 sleep 7 r/w 0x02 0 = enable dac output, 1 = disable dac output (sleep). txdac quad-switch mode of operation 0x08 dac-dec [1:0] r/w 0x00 0x 00 = normal baseband mode. 0x01 = return-to-zero mode. 0x02 = mix mode. dci phase alignment status dci_pre_ph0 2 r 0 0 = dci rising edge is after the pre delayed version of the phase 0 sampling edge. 1 = dci rising edge is before the pre delayed version of the phase 0 sampling edge. 0x0c dci_pst_ph0 0 r 0 0 = dci rising edge is after the post delayed version of the phase 0 sampling edge. 1 = dci rising edge is before the post delayed version of the phase 0 sampling edge.
AD9739A rev. 0 | page 26 of 44 address (hex) name bit r/w default setting comments data receiver controller configuration rcvr_flg_rst 2 w 0 data receiver controller flag reset. write 1 followed by 0 to reset flags. rcvr_loop_on 1 r/w 1 0 = disable, 1 = enable. when enabled, the data receiver controller generates an irq; it falls out of lock and automatically begins a search/track routine. 0x10 rcvr_cnt_ena 0 r/w 0 data receiver cont roller enable. 0 = disable, 1 = enable. data receiver controller_data sample delay value 0x11 smp_del[1:0] [7:6] r/w 11 0x12 smp_del[9:2] [7:0] r/w 0x25 controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample data. leave at the default setting of 167, which represents the midpoint of the delay line. controller disabled: the value sets the actual value of the delay line. data receiver controller_dci delay value/window and phase rotation dci_del[3:0] [7:4] r/w 0111 refer to the dci_del description in register 0x14. 0x13 fine_del_skew [3:0] r/w 0001 a 4-bit value sets the difference (that is, window) for the dci pre and post sampling clocks. leave at the default value of 1 for a narrow window. 0x14 dci_del[9:4] [5:0] r/w 001010 controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by th e state machine to sample the dci input. leave at the default setting of 167, which represents the midpoint of the delay line. controller disabled: the value sets the actual value of the delay line. data receiver controller_delay line status 0x19 smp_del[1:0] [1:0] r 00 0x1a smp_del[9:2] [7:0] r 0x00 0x1b dci_del[1:0] [1:0] r 00 0x1c dci_del[9:2] [7:0] r 0x00 the actual value of the dci and data delay lines determined by the data receiver controller (when enabled) after the state machine completes its search and enters track mode. note that these values should be equal. data receiver controller lock/tracking status rcvr_trk_on 3 r 0 0 = tracking not established, 1 = tracking established. rcvr_lst 1 r 0 0 = controller has not lost lock, 1 = controller has lost lock. 0x21 rcvr_lck 0 r 0 0 = controller is not locked, 1 = controller is locked. clk input common mode dir_p 4 r/w 0 0x22 clkp_offset[3:0] [3:0] r/w 0000 dir_n 4 r/w 0 0x23 clkn_offset[3:0] [3:0] r/w 0000 dir_p and dir_n. 0 = vcm at the dacclk_p input decreases with the offset value. 1 = vcm at the dacclk_p input increases with the offset value. clkx_offset sets the magnitude of the offset for the dacclk_p and dacclk_n inputs. for optimum performance, set to 1111. mu controller configuration and status cmp_bst 5 r/w 0 0x24 phs_det auto_en 4 r/w 0 phase detector enable and boost bias bits. note that both bits should always be set to 1 to enable these functions. 0x25 mu_duty auto_en 7 r/w 0 mu controller duty cycle enable. note that this bit should al ways be set to 1 to enable. slope 6 r/w 1 mu controller phase slope lock. 0 = negative slope, 1 = positive slope. note that a setting of 0 is recommended for best ac performance. 0x26 mode[1:0] [5:4] r/w 00 sets the mu controller mode of operation. 00 = search and track (recommended). 01 = search only. 10 = track. read 3 r/w 0 set to 1 to read the current value of the mu delay line in.
AD9739A rev. 0 | page 27 of 44 address (hex) name bit r/w default setting comments gain[1:0] [2:1] r/w 01 sets the mu controller tracking gain. recommended to leave at the default 01 setting. enable 0 r/w 0 0 = enable the mu controller. 1 = disable the mu controller. mudel[0] 7 r/w 0 the lsb of the 9-bit mudel setting. srch_mode[1:0] [6:5] r/w 0 sets the direction in which the mu controller searches (from its initial mudel setting) for the optimum mu delay line setting that corresponds to the desired phase/slope setting (that is, set_phs and slope ). 00 = down. 01 = up. 10 = down/up (recommended). 0x27 set_phs[4:0] [4:0] r/w 0 sets the target phase that the mu controller locks to with a maximum setting of 16. a setting of 4 (that is, 00100) is recommended for optimum ac performance. w 0x00 with enable (bit 0, register 0x26) set to 0, this 9-bit value represents the value that the mu delay is set to. note that the maximum value is 432. with enable set to 1, this value represents the mu delay value at which the controller begins its search. setting this value to the delay line midpoint of 216 is recommended. 0x28 mudel[8:1] [7:0] r 0x00 when read (bit 3, register 0x26) is set to 1, the value read back is equal to the value written into the register when enable = 0 or the value that the mu controller locks to when enable = 1. search_tol 7 r/w 0 0 = not exact (can find a phase within two values of the desired phase). 1 = finds the exact phase that is targeted (optimal setting). retry 6 r/w 0 0 = stop the search if the correct value is not found, 1 = retry the search if the correct value is not found. contrst 5 r/w 0 controls whether the controller resets or continues when it does not find the desired phase. 0 = continue (optimal setting), 1 = reset. 0x29 guard[4:0] 5 r/w 01011 sets a guard band from the beginning and end of the mu delay line which the mu controller does not enter into unless it does not find a valid phase outside the guard band (optimal value is decimal 11 or 0x0b). mu_lst 1 r 0 0 = mu controller has not lost lock. 1 = mu controller has lost lock. 0x2a mu_lkd 0 r 0 0 = mu controller is not locked. 1= mu controller is locked. part id 0x35 part_id [7:0] r 0x24
AD9739A rev. 0 | page 28 of 44 theory of operation the AD9739A is a 14-bit txdac with a specified update rate of 1.6 gsps to 2.5 gsps. figure 74 shows a top-level functional diagram of the AD9739A. a high performance txdac core delivers a signal dependent, differential current (nominal 10 ma) to a balanced load referenced to ground. the frequency of the clock signal appearing at the AD9739A differential clock receiver, dacclk, sets the txdacs update rate. this clock signal, which serves as the master clock, is routed directly to the txdac as well as to a clock distribution block that generates all critical internal and external clocks. the AD9739A includes two 14-bit lvds data ports (db0 and db1) to reduce the data interface rate to ? the txdac update rate. the host processor drives deinterleaved data with offset binary format onto the db0 and db1 ports, along with an embedded dci clock that is synchronous with the data. because the interface is double data rate (ddr), the dci clock is essentially an alternating 0-1 bit pattern with a frequency equal to ? the txdac update rate (f dac ). to simplify synch- ronization with the host processor, the AD9739A passes an lvds clock output (dco) that is also equal to the dci frequency. the AD9739A data receiver controller generates an internal sampling clock for the ddr receiver such that the data instance sampling is optimized. when enabled and configured properly for track mode, it ensures proper data recovery between the host and the AD9739A clock domains. the data receiver controller has the ability to track several hundreds of ps of drift between these clock domains, typically caused by supply and temperature variation. as mentioned, the host processor provides the AD9739A with a deinterleaved data stream such that the db0 and db1 data ports receive alternating samples (that is, odd/even data streams). the AD9739A data assembler is used to reassemble (that is, multiplex) the odd/even data streams into their original order before delivery into the txdac for signal reconstruction. the pipeline delay from a sample being latched into the data port to when it appears at the dac output is on the order of 78 () dacclk cycles. the AD9739A includes a delay lock loop (dll) circuit controlled via a mu controller to optimize the timing hand-off between the AD9739A digital clock domain and txdac core. besides ensuring proper data reconstruction, the txdacs ac performance is also dependent on this critical hand-off between these clock domains with speeds of up to 2.5 gsps. once properly initialized and configured for track mode, the dll maintains optimum timing alignment over temperature, time, and power supply variation. a spi interface is used to configure the various functional blocks as well as monitor their status for debug purposes. proper operation of the AD9739A requires that controller blocks be initialized upon power-up. a simple spi initialization routine is used to configure the controller blocks (see table 11 ). an irq output signal is available to alert the host should any of the controllers fall out of lock during normal operation. the following sections discuss the various functional blocks in more detail as well as their implications when interfacing to external ics and circuitry. while a detailed description of the various controllers (and associated spi registers used to configure and monitor) is also included for completeness, the recommended spi boot procedure can be used to ensure reliable operation. lvds ddr receiver dci sdo sdio s clk cs dacclk dco db0[13:0] db1[13:0] clk distribution (div-by-4) data controller 4-to-1 data assembler spi reset dll (mu controller) lvds ddr receiver data latch ioutn ioutp vref i120 irq 1.2v dac bias AD9739A txdac core 09616-077 figure 74. functional block diagram of the AD9739A
AD9739A rev. 0 | page 29 of 44 lvds data port interface the AD9739A supports input data rates from 1.6 gsps to 2.5 gsps using dual lvds data ports. the interface is source synchronous and double data rate (ddr) where the host provides an embedded data clock input (dci) at f dac /4 with its rising and falling edges aligned with the data transitions. the data format is offset binary; however, twos complement format can be realized by reversing the polarity of the msb differential trace. as shown in figure 75 , the host feeds the AD9739A with deinterleaved input data into two 14-bit lvds data ports (db0 and db1) at ? the dac clock rate (that is, f dac /2). the AD9739A internal data receiver controller then generates a phase shifted version of dci to register the input data on both the rising and falling edges. lvds ddr receiver dci dco db0[13:0] div-by-4 data controller lvds ddr receiver db1[13:0] AD9739A host processor lvds ddr driver 14 2 f data = f dac /2 f dco = f dac /4 f dac f dci = f dac /4 14 2 1 2 1 2 data deinterleaver even data samples odd data samples 09616-078 figure 75. recommended digital interface between the AD9739A and host processor as shown in figure 76 , the dci clocks edges must be coincident with the data bit transitions with minimum skew, jitter, and intersymbol interference. to ensure coincident transitions with the data bits, the dci signal should be implemented as an additional data line with an alternating (010101) bit sequence from the same output drivers used for the data. maximizing the opening of the eye in both the dci and data signals improves the reliability of the data port interface. differential controlled impedance traces of equal length (that is, delay) should also be used between the host processor and AD9739A input to limit bit-to-bit skew. the maximum allowable skew and jitter out of the host processor with respect to the dci clock edge on each lvds port is calculated as follows: maxskew + jitter = period(ns) ? validwindow (ps) ? guard = 800 ps ? 344 ps ? 100 ps = 356 ps where validwindow (ps) is represented by t va l i d and guard is represented by t guard in figure 76 . the minimum specified lvds va lid window is 344 ps, and a guard band of 100 ps is recommended. therefore, at the maxi- mum operating frequency of 2.5 gsps, the maximum allowable fpga and pcb bit skew plus jitter is equal to 356 ps. for synchronous operation, the AD9739A provides a data clock output, dco, to the host at the same rate as dci (that is, f dac /4) to maintain the lowest skew variation between these clock domains. the host processor has a worst case skew between dco and dci that is both implementation and process dependent. this worst case skew can also vary an additional 30% over temperature and supply corners. the delay line within the data receiver controller can track a 1.5 ns skew variation after initial lock. while it is possible for the host to have an internal pll that generates a synchronous f dac /4 from which the dci signal is derived, digital implementations that result in the shortest propagation delays result in the lowest skew variation. the data receiver controller is used to ensure proper data hand- off between the host and AD9739A internal digital clock domains. the circuit shown in figure 77 functions as a delay lock loop in which a 90 o phase shifted version of the dci clock input is used to sample the input data into the ddr receiver registers. this ensures that the sampling instance occurs in the middle of the data pattern eyes (assuming matched dci and dbx[13:0] delays). note that, because the dci delay and sample delay clocks are derived from the div-by-4 circuitry, this 90 phase relationship holds as long as the delay settings (that is, dci_del, smp_del) are also matched. db0[13:0] a nd db1[13:0] dci t valid t valid + t guard 2 1 /f dac max skew + jitter 09616-079 figure 76. lvds data port timing requirements
AD9739A rev. 0 | page 30 of 44 fine delay ddr ff dbx[13:1] data receiver controller dci delay sample delay dci pre post sample dci window pre dci window post dci window sample data to core delay delay fine delay fine delay state machine/ tracking loop elastic fifo ddr ff ddr ff ddr ff ddr ff 180 0 f dac div-by-4 90 270 delay delay ddr ff ddr ff dci delay path sample delay path dco 09616-080 f igure 77. top level diagram of the data receiver controller th e div-by-4 circuit generates four clock phases that serve as inputs to the data receiver controller. all of the ddr registers in the data and dci paths operate on both clock edges; however, for clarity purposes, only the phases (that is, 0 o and 90 o ) corresponding to the positive edge of each path are shown. one of the div-by-4 phases is used to generate the dco signal; therefore, the phase relationship between dco and clocks fed into the controller remains fixed. note that it is this attribute that allows possible factory calibration of images and clock spurs attributed to f dac /4 modulation of the critical dac clock. on ce this data has been successively sampled into the first set of registers, an elastic fifo is used to transfer the data into the AD9739A clock domain. to continuously track any phase variation between the two clock domains, the data receiver controller should always be enabled and placed into track mode (register 0x10, bit 1 and bit 0). tracking mode operates continuously in the background to track delay variations between the host and AD9739A clock domains. it does so by ensuring that the dci signal is sampled within a very narrow window defined by two internally generated clocks (that is, pre and pst), as shown in figure 78 . note that proper sampling of the dci signal can also be confirmed by monitoring the status of dci_pre_ph0 (register 0x0c, bit 2) and dci_pst_ph0 (register 0x0c, bit 0). if the delay settings are correct, the state of dci_ pre_ph0 should be 0, and the state of dci_pst_ph0 should be 1. dci fine delay pst fine delay pre fine_del_skew 09616-081 fi gure 78. pre- and post-delay sampling diagram the skew or window width (fine_del_skew) is set via register 0x13, bits[3:0], with a maximum skew of approx- imately 300 ps and resolution of 20 ps. it is recommended that the skew be set to 60 ps (that is, register 0x13 = 0x72) during initialization. note that the skew setting also affects the speed of the controller loop, with tighter skew settings corresponding to longer response time. data receiver controller initialization description the data controller should be initialized and placed into track mode as the second step in the spi boot sequence. the following steps are recommended for the initialization of the data receiver controller: 1. set fine_del_skew to 2 for a larger dci sampling window (register 0x13 = 0x72). note that the default dci_del and smp_del settings of 167 are optimum. 2. disable the controller before enabling (that is, register 0x10 = 0x00). 3. enable the rx controller in two steps: register 0x10 C 0x02 followed by register 0x10 = 0x03. 4. wait 135 k clock cycles.
AD9739A rev. 0 | page 31 of 44 5. read back register 0x21 and confirm that it is equal to 0x05 to ensure that the dll loop is locked and tracking. 6. read back the dci_del value to determine whether the value falls within a user defined tracking guard band. if it does not, go back to step 2. once the controller is enabled during the initial spi boot process (see table 12 ), the controller enters a search mode where it seeks to find the closest rising edge of the dci clock (relative to a delayed version of an internal f dac /4 clock) by simultaneously adjusting the delays in the clocks used to register the dci and data inputs. a state machine searches above and below the initial dci_del value. the state machine first searches for the first rising edge above the dci_del and then searches for the first rising edge below the dci_del value. the state machine selects the closest rising edge and then enters track mode. it is recommended that the default midpoint delay setting (that is, decimal 167) for the dci_del and smp_del bits be kept to ensure that the selected edge remains closest to the delay line midpoint, thus providing the greatest range for tracking timing variations and preventing the controller from falling out of lock. the adjustable delay span for these internal clocks (that is, dci and sample delay) is nominally 4 ns. the 10-bit delay value is user programmable from the decimal equivalent code (0 to 334) with approximately 12 ps/lsb resolution via the dci_del and smp_del registers (register 0x13 and register14). when the controller is enabled, it overwrites these registers with the delay value it converges upon. the minimum difference between this delay value and the minimum/maximum values (that is, 0 and 334) represents the guard band for tracking. therefore, if the controller initially converges upon a dci_del and smp_del value between 80 and 254, the controller has a guard band of at least 80 code (approximately 1 ns) to track phase variations between the clock domains. upon initialization of the AD9739A, a certain period of time is required for the data receiver controller to establish a lock of the dci clock signal. note that, due to its dependency on the mu controller, the data receiver controller should be enabled only after the mu controllers have been enabled and established lock. all of the internal controllers operate at a submultiple of the dac update rate. the number of f dac clock cycles required to lock onto the dci clock is typically 70 k clock cycles but can be up to 135 k clock cycles. during the spi initialization process, the user has the option of polling register 0x21 (bit 0, bit 1, and bit 3) to determine if the data receiver controller is locked, has lost lock, or has entered into track mode before completing the boot sequence. alternatively, the appropriate irq bit (register 0x03 and register 0x04) can be enabled such that an irq output signal is generated upon the controller establishing lock. the data receiver controller can also be configured to generate an interrupt request (irq) upon losing lock. losing lock can be caused by disruption of the main dac clock input or loss of a power supply rail. to service the interrupt, the host can poll the rcvr_lck bit to determine the current state of the controller. if this bit is cleared, the search/track procedure can be restarted by setting the rcvr_loop_on bit in register 0x10, bit 1. after waiting the required lock time, the host can poll the rcvr_lck bit to see if it has been set. before leaving the interrupt routine, the rcvr_flg_rst bit should be reset by writing a high followed by a low. lvds driver and receiver input the AD9739A features an lvds-compatible driver and receivers. the lvds driver output used for the dco signal includes an equivalent 200 source resistor that limits its nominal output voltage swing to 200 mv when driving a 100 load. the dco output driver can be powered down via register 0x1, bit 5. an equivalent circuit is shown in figure 79 dco_n vss v dd33 dco_p v+ v+ v? v? 100 ? vcm 100 ? esd esd 0 9616-082 figure 79. equivalent lvds output vss v dd33 dci_p dbx[13:0] p dci_n dbx[13:0]n 100 ? esd esd 09616-083 figure 80. equivalent lvds input the lvds receivers include 100 termination resistors, as shown in figure 80 . these receivers meet the ieee-1596.3-1996 reduced swing specification (with the exception of input hysteresis, which cannot be guaranteed over all process corners). figure 81 and table 10 show an example of nominal lvds voltage levels seen at the input of the differential receiver with resulting common-mode voltage and equivalent logic level. note that the AD9739A lvds inputs do not include fail-safe capability; hence, any unused input should be biased with an external circuit or static driver. the lvds receivers can be powered-down via register 0x01, bit 4.
AD9739A rev. 0 | page 32 of 44 lvds inputs (no fail-safe) v p lvds receiver gnd 100 ? v n v p, n v com = ( v p + v n )/2 logic bit equivalent v p v n v p v n example 1.4v 1.0v 0.4v ?0.4v 0v logic 1 logic 0 09616-084 figure 81. lvds data input levels table 10. example of lvds input levels applied voltages resulting differenital voltage resulting common- model voltage v p v n v p, n v com logic bit binary equivalent 1.4 v 1.0 v +0.4 v 1.2 v 1 1.0 v 1.4 ?0.4 v 1.2 v 0 1.0 v 0.8 v +200 mv 900 mv 1 0.8 v 1.0 v ?200 mv 900 mv 0 mu controller a delay lock loop (dll) is used to optimize the timing between the internal digital and analog domains of the AD9739A such that data is successfully transferred into the txdac core at rates of up to 2.5 gsps. as shown in figure 82 , the dac clock is split into an analog and a digital path with the critical analog path leading to the dac core (for minimum jitter degradation) and the digital path leading to a programmable delay line. note that the output of this delay line serves as the master internal digital clock from which all other internal and external digital clocks are derived. the amount of delay added to this path is under the control of the mu controller, which optimizes the timing between these two clock domains and continuously tracks any variation (once in track mode) to ensure proper data hand-off. 14-bi t data 14-bi t data ioutp ioutn digital circuitry analog circuitry mu delay dac clock phase detector mu delay controller 09616-085 fi gure 82. mu delay controller block diagram th e mu controller adusts the timing relationship between the digital and analog domains via a tapped digital delay line having a nominal total delay of 864 ps. the delay value is program- mable to a 9-bit resolution (that is, 0 to 432 decimal) via the mudel register, resulting in a nominal resolution of 2 ps/lsb. because a time delay maps to a phase offset for a fixed clock frequency, the control loop essentially compares the phase relationship between the two clock domains and adusts the phase (that is, via a tapped delay line) of the digital clock such that it is at the desired fixed phase offset (set_phs) from the critical analog clock. 0 2 4 6 8 10 12 14 16 18 0 40 80 120 160 200 240 280 320 360 400 440 search starting location guard band guard band mu delay mu phase desired phase 09616-086 fi gure 83. typical mu phase characteristic plot at 2.4 gsps figure 83 maps the typical mu phase characteristic at 2.4 gsps versus the 9-bit digital delay setting (mudel). the mu phase scaling is such that a value of 16 corresponds to 180 degrees. the critical keep-out window between the digital and analog domains occurs at a value of 0 (but can extend out to +2 depending on the clock rate). the target mu phase (and slope) is selected to provide optimum ac performance while ensuring that the mu controller for any d evice can establish and maintain lock. while the mu phase characteristics can vary among devices, a slope/phase setting of 4 has been verified to ensure robust operation and optimum ac performance for 1.6 gsps to 2.5 gsps operation. after the mu controller completes its search and establishes lock on the target mu phase, it attempts to maintain a constant timing relationship between the two clock domains over the specified temperature and supply range. if the mu controller requests a mu delay setting that exceeds the tapped delay line range (that is, 0 or 432), the mu controller can lose lock, causing possible system disruption (that is, can generate irq or restart the search). to avoid this scenario, symmetrical guard bands are recommended at each end of the mu delay range. the guard band scaling is such that one lsb of guard[4:0] corres- ponds to eight lsbs of mudel. the recommended guard band setting of 11 (that is, register 0x29 = 0xcb) corresponds to 88 lsbs, thus providing sufficient margin.
AD9739A rev. 0 | page 33 of 44 mu controller initialization description the mu controller must be initialized and placed into track mode as a first step in the spi boot sequence. the following steps are required for initialization of the mu controller. note that the AD9739A data sheet specifications and characterization data are based on the following mu controller settings: 1. turn on the phase detector with boost (register 0x24 = 0x30). 2. enable the mu delay controller duty-cycle correction circuitry and specify the recommended slope for phase. (that is, register 0x25 = 0x80 corresponds to a negative slope). 3. specify search/track mode with a recommended target phase, set_phs, of 4 and an initial mudel[8:0] setting of 216 (register 0x27 = 0x44 and register 0x28 = 0x6c). 4. set search tolerance to exact and retry if the search fails its initial attempt. also, set the guard band to the recom- mended setting of 11 (register 0x29 = 0xcb). 5. set the mu controller tracking gain to the recommended setting and enable the mu controller state machine (register 0x26 = 0x03). upon completion of the last step, the mu controller begins a search algorithm that starts with an initial delay setting specified by the mudel register (that is, 216, which corresponds to the midpoint of the delay line). the initial search algorithm works by sweeping through different mu delay values in an alternating manner until the desired phase (that is, a set_phs of 4) is exactly measured. when the desired phase is measured, the slope of the phase measurement is then calculated and compared against the specified slope (slope = negative). if everything matches, the search algorithm is finished. if not, the search continues in both directions until an exact match can be found or a programmable guard band is reached in one of the directions. when the guard band is reached, the search still continues but only in the opposite direction. if the desired phase is not found before the guard band is reached in the second direction, the search changes back to the alternating mode and continues looking within the guard band. the typical locking time for the mu controller is approximately 180 k dac cycles (at 2 gsps ~ 75 s). the search fails if the mu delay controller reaches the end- points. the mu controller can be configured to retry (register 0x29, bit 6) the search or stop. for applications that have a microcontroller, the preferred approach is to poll the mu_lkd status bit (register 0x2a, bit 0) after the typical locking time has expired. this method allows the system controller to check the status of other system parameters (that is, power supplies and clock source) before reattempting the search (by writing 0x03 to register 26). for applications not having polling capa- bility, the mu controller state machine should be reconfigured to restart the search in hopes that the systems condition that did not cause locking on the first attempt has disappeared. once the mu delay value is found that exactly matches the desired mu phase setting and slope (that is, 4 with a negative. slope), the mu controller goes into track mode. in this mode, the mu controller makes slight adjustments to the delay value to track any variations between the two clock paths due to temperature, time, and supply variations. two status bits, mu_lkd (register 0x2a, bit 0) and mu_lst (register 0x2a, bit 1) are available to the user to signal the existing status control loop. if the current phase is more than four steps away from the desired phase, the mu_lkd bit is cleared, and the mu_lst bit is set if the lock acquired was previously set. should the phase deviation return to within three steps, the mu_lkd bit is set again while the mu_lst is cleared. note that this sort of event may occur if the main clock input (that is, dacclk) is disrupted or the mu controller exceeds the tapped delay line range (that is, <0 or >432). if lock is lost, the mu controller has the option of remaining in the tracking loop or resetting and starting the search again via the contrst bit (register 0x29, bit 5). continued tracking is the preferred state because it is the least disruptive to a system in which the AD9739A temporarily loses lock. the user can poll the mu delay and phase value by first setting the read bit high (register 0x26, bit 3). once the read bit is set, the mudel[8:0] bits and the set_phs[4:0] bits (register 0x27 and register 0x28) that the controller is currently using can be read. interrupt requests the AD9739A can provide the host processor with an interrupt request output signal (irq) that indicates that one or more of the AD9739A internal controllers have achieved lock or lost lock. these controllers include the mu, data receiver, and synchronization controllers. the host can then poll the irq status register (register 0x04) to determine which controller has lost lock. the irq output signal is an active high output signal available on pin f13. if used, its output should be connected via a 10 k pull-up resistor to vdd33. each irq is enabled by setting the enable bits in register 0x03, which purposely has the same bit mapping as the irq status bits in register 0x04. note that these irq status bits are set only when the controller transitions from a false to true state. hence, it is possible for the x_lck_irq and x_lst_irq status bits to be set when a controller temporarily loses lock but is able to reestablish lock before the irq is serviced by the host. in this case, the host should validate the present status of the suspect controller by reading back its current status bits, which are available in register 0x21 and/or register 0x2a. based on the status of these bits, the host can take appropriate action, if required, to reestablish lock. to clear an irq after servicing, it is necessary to reset relevant bits in register 0x03 by writing 0 followed by another write of 1 to reenable. a detailed diagram of the interrupt circuitry is shown in figure 84 .
AD9739A rev. 0 | page 34 of 44 int(n) q d int source spi isr read data (pin f13) spi write int source spi address data = 1 imr sclk spi data 09616-087 figure 84. interrupt request circuitry table 11. interrupt request registers address (hex) bit description 3 it is also possible to use the irq during the AD9739A initial- ization phase after power-up to determine when the mu and data receiver controllers have achieved lock. for example, before enabling the mu controller, the mu_lck_en bit can be set and the irq output signal monitored to determine when lock has been established before continuing in a similar manner with the data receiver controllers. note that the relevant lck bit should be cleared before continuing to the next controller. after all controllers are locked, the lost lock enable bits (that is, x_lst_en) should be set. mu_lst_en 2 mu_lck_en 1 rcv_lst_en 0x03 0 rcv_lck_en 3 mu_lst_irq 2 mu_lck_irq 1 rcv_lst_irq 0x04 0 rcv_lck_irq 3 rcvr_trk_on 1 rcvr_lst 0x21 0 rcvr_lck 1 mu_lst 0x2a 0 mu_lkd
AD9739A rev. 0 | page 35 of 44 analog interface considerations analog modes of operation the AD9739A uses the quad-switch architecture shown in figure 85 . the quad-switch architecture masks the code- dependent glitches that occur in a conventional two-switch dac. figure 86 compares the waveforms for a conventional dac and the quad-switch dac. in the two-switch architecture, a code-dependent glitch occurs each time the dac switches to a different state (that is, d1 to d2). this code-dependent glitching causes an increased amount of distortion in the dac. in quad-switch architecture (no matter what the codes are), there are always two switches transitioning at each half clock cycle, thus eliminating the code-dependent glitches. however, a constant glitch occurs at 2 dacclk because half the internal switches change state on the rising dacclk edge while the other half change state on the falling dacclk edge. v g 1 v dd ioutp ioutn v g 1 g 4 v g 3v g 2 dacclk_x clk latches dbx[13:0] v g 2 v g 3 v g 4 v 09616-088 figure 85. AD9739A quad-switch architecture inpu t data dacclk_x two-switch dac output four-switch dac output (normal mode) t d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t 09616-089 figure 86. two-switch and quad-switch dac waveforms another attribute of the quad-switch architecture is that it also enables the dac core to operate in one of the following three modes: normal mode, mix mode, and return-to-zero (rz ) mode. the mode is selected via spi register 0x08, bits[1:0] with normal mode being the default value. in the mix mode, the output is effectively chopped at the dac sample rate. this has the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the dac sample rate, thus improving the output power of these images. the rz mode is similar to the analog mix mode, except that the intermediate data samples are replaced with midscale values. inpu t data dacclk_x four-switch dac output ( f s mix mode) four-switch dac output (return to zero mode) d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 ?d 6 ?d 7 ?d 8 ?d 9 ?d 10 d 6 d 7 d 8 d 9 d 10 ?d 1 ?d 2 ?d 3 ?d 4 ?d 5 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t t 09616-090 figure 87. mix-mode and rz dac waveforms figure 87 shows the dac waveforms for both the mix mode and the rz mode. note that the disadvantage of the rz mode is the 6 db loss of power to the load because the dac is only functioning for ? the dac update period. this ability to change modes provides the user the flexibility to place a carrier anywhere in the first three nyquist zones, depending on the operating mode selected. switching between the analog modes reshapes the sinc roll-off inherent at the dac output. the maximum amplitude in all three nyquist zones is impacted by this sinc roll-off, depending on where the carrier is placed (see figure 88 ). as a practical matter, the usable bandwidth in the third nyquist zone becomes limited at higher dac clock rates (that is, >2 gsps) when the output bandwidth of dac core and the interface network (that is, balun) contributes to additional roll-off. frequency (hz) 0fs 1.50fs 1.25fs 1.00fs 0.75fs 0.50fs 0.25fs ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 first nyquist zone second nyquist zone third nyquist zone mix mode rz mode normal mode 09616-091 figure 88. sinc roll-off for each analog operating mode
AD9739A rev. 0 | page 36 of 44 clock input considerations d d q v cc v ee v t q v ref 50 ? 50? 50? 50? 50? dacclk_p dacclk_n 100 ? 10nf 10nf adclk914 AD9739A 10nf 10nf 50? 09616-092 figure 89. adclk914 interface to the AD9739A clk input vco pll adf4350 fref 1.8v p-p v vco 1nf 1nf AD9739A 3.9nh rf out a? rf out a+ rf out a? rf out a+ 100 ? dacclk_p dacclk_n div-by-2 n n = 0 ? 4 09616-093 figure 90. adf4350 interface to the AD9739A clk input the quality of the clock source and its drive strength are important considerations in maintaining the specified ac performance. the phase noise and spur characteristics of the clock source should be selected to meet the target application requirements. phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. it can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 log10(f out /f clk ) when the dac clock path contribution, along with thermal and quantization effects, are negligible. the AD9739A clock receiver provides optimum jitter performance when driven by a fast slew rate originating from the lvpecl or cml output drivers. for a low jitter sinusoidal clock source, the adclk914 can be used to square-up the signal and provide a cml input signal for the AD9739A clock receiver. note that all specifications and characterization presented in the data sheet are with the adclk914 driven by a high quality rf signal generator with the clock receiver biased at a 800 mv level. figure 90 shows a clock source based on the adf4350 low phase noise/jitter pll. the adf4350 can provide output frequencies from 140 mhz up to 4.4 ghz with jitter as low as 0.5 ps rms. each single-ended output can provide a squared-up output level that can be varied from ?4 dbm to +5 dbm allowing for >2 v p-p output differential swings. the adf4350 also includes an additional cml buffer that can be used to drive another AD9739A device. esd dacclk_p dacclk_n vddc vssc clkx_offset dir_x = 0 clkx_offset dir_x = 0 4-bit pmos iout array 4-bit nmos iout array 09616-094 fi gure 91. clock input and common-mode control th e AD9739A clock receiver features the ability to indepen- dently adjust the common-mode level of its inputs over a span of 100 mv centered about is mid-supply point (that is, vddc/2) as well as an offset for hysteresis purposes. figure 91 shows the equivalent input circuit of one of the inputs. esd diodes are not shown for clarity purposes. it has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 v. this can be achieved by writing a 0x0f (corresponding to a ?15) setting to both cross controller registers (that is, register 0x22 and register 0x23).
AD9739A rev. 0 | page 37 of 44 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 1 3 5 7 9 11 13 15 offset code common mode (v) clkp clkn 09616-095 f igure 92. common-mode voltage with respect to clkp_offset/clkn_offset and dir_p/dir_n v oltage reference the AD9739A output current is set by a combination of digital control bits and the i120 reference current, as shown in figure 93 . current scaling fsc[9:0] ad9739 dac ifull-scale 10k ? 1nf v ref i120 vssa i120 v bg 1.2v + ? 09616-096 figure 93. voltage reference circuit the reference current is obtained by forcing the band gap voltage across an external 10 k resistor from i120 (pin b14) to ground. the 1.2 v nominal band gap voltage (vref) generates a 120 a reference current in the 10 k resistor. note the following constraints when configuring the voltage reference circuit: x both the 10 k resistor and 1 nf bypass capacitor are required for proper operation. x adjusting the dacs output full-scale current, i outfs , from its default setting of 20 ma should be performed digitally. x the AD9739A is not a multiplying dac. modulating the reference current, i120, with an ac signal is not supported. x the band gap voltage appearing at the vref pin must be buffered for use with an external circuitry because its output impedance is approximately 5 k. x an external reference can be used to overdrive the internal reference by connecting it to the vref pin. i outfs can be adjusted digitally over 8.7 ma to 31.7 ma by using fsc[9:0] (register 0x06 and register 0x07). the following equation relates i outfs to the fsc[9:0] register, which can be set from 0 to 1023. i outfs = 22.6 fsc [9:0]/1000 + 8.7 (1) note that a default value of 0x200 generates 20 ma full scale, which is used for most of the characterization presented in this data sheet (unless noted otherwise). analog outputs equivalent dac output and transfer function the AD9739A provides complementary current outputs, ioutp and ioutn, that source current into an external ground reference load. figure 94 shows an equivalent output circuit for the dac. note that, compared to most current output dacs of this type, the AD9739A outputs exhibit a slight offset current (that is, i outfs /16), and the peak differential ac current is slightly below i outfs /2 (that is, 15/32 i outfs ). 17/32 i outfs i peak = 15/32 i outfs ac 70 ? 2.2pf i outfs = 8.6 ? 31.2ma 17/32 i outfs 09616-097 figure 94. equivalent dac output circuit as shown in figure 94 , the dac output can be modeled as a pair of dc current sources that source a current of 17/32 i outfs to each output. a differential ac current source, i peak, is used to model the signal-dependent nature of the dac output. the polarity and signal dependency of this ac current source are related to the digital code by the following equation: f ( code ) = ( daccode ? 8192)/8192 (2) ?1 < f ( code ) < 1 (3) where daccode = 0 to 16,383 (decimal). because i peak can swing (15/32) i outfs , the output currents measured at ioutp and ioutn can span from i outfs /16 to i outfs . however, because the ac signal-dependent current component is complementary, the sum of the two outputs is always constant (that is, ioutp + ioutn = (34/32) i outfs ). the code-dependent current measured at the ioutp (and ioutn) output is as follows: i outp = 17/32 i outfs + 15/32 i outfs f ( code ) (4) ioutn = 17/32 i outfs ? 15/32 i outfs f ( code ) (5) figure 95 shows the ioutp vs. daccode transfer function when i outfs is set to 19.65 ma.
AD9739A rev. 0 | page 38 of 44 20 18 10 12 14 16 output current (ma) 8 6 4 2 0 0 4096 8192 12,288 dac code 16,384 09616-098 if the AD9739A is programmed for i outfs = 20 ma, its peak ac current is 9.375 ma and its peak power delivered to the equivalent load is 2.2 mw (that is, p = i 2 r). because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally; therefore, the output load receives 1.1 mw or 0.4 dbm. to calculate the rms power delivered to the load, the following must be considered: ? peak-to-rms of the digital waveform ? any digital backoff from digital full scale ? the dacs sinc response and nonideal losses in external network for example, a reconstructed sine wave with no digital backoff ideally measures ?2.6 dbm because it has a peak-to-rms ratio of 3 db. if a typical balun loss of 0.4 dbm is included, ?3 dbm of actual power can be expected in the region where the dacs sinc response has negligible influence. increasing the output power is best accomplished by increasing i outfs , although any degradation in linearity performance must be considered acceptable for the target application. figure 95. gain curve for fsc[9: 0] = 512, dac offset = 1.228 ma peak dac output power capability the maximum peak power capability of a differential current output dac is dependent on its peak differential ac current, i peak , and the equivalent load resistance it sees. because the AD9739A includes a differential 70 resistance, it is best to use a doubly terminated external output network similar to what is shown in figure 97 . in this case, the equivalent load seen by the dacs ac current source is 25 . i peak = 15/32 i outfs ac 70 ? i outfs = 8.6 ? 31.2ma 180 ? r load = 50 ? r source = 50 ? lossless balun 1:1 09616-099 figure 96. equivalent circuit for determining maximum peak power to a 50 load
AD9739A rev. 0 | page 39 of 44 output stage configuration the AD9739A is intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, docsis cmts) and/or high if/rf signal generation. optimum ac performance can only be realized if the dac output is configured for differential (that is, balanced) operation with its output common-mode voltage biased to analog ground. the output network used to interface to the dac should provide a near 0 dc bias path to analog ground. any imbalance in the output impedance between the ioutp and ioutn pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. component selection and layout are critical in realizing the AD9739As performance potential. mini-circuits ? tc1-33-75g+ 90? 90? ioutp ioutn 70? 09616-100 figure 97. recommended balun for wi deband applications with upper bandwidths of up to 2.2 ghz most applications requiring balanced-to-unbalanced conversion can take advantage of the ruthroff 1:1 balun configuration shown in figure 97 . this configuration provides excellent amplitude/phase balance over a wide frequency range while providing a 0 dc bias path to each dac output. also, its design provides exceptional bandwidth and can be considered for applications requiring signal reconstruction of up to 2.2 ghz. the characterization plots shown in this data sheet are based on the AD9739A evaluation board, which uses this configuration. figure 98 compares the measured frequency response for normal and mix mode using the AD9739A evaluation board vs. the ideal frequency response. ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 power (dbc) ?12 ?9 ?6 ?3 0 0 500 1000 1500 2000 2500 3000 3500 frequency (mhz) ideal baseband mode mix mode tc1-33-75g baseband tc1-33-75g ideal mix mode 09616-101 figure 98. measured vs. ideal frequency response for normal (baseband) and mix-mode operation using a tc1-33-75g transformer on the AD9739A evb figure 99 shows an interface that can be considered when interfacing the dac output to a self-biased differential gain block. the inductors shown serve as rf chokes (l) that provide the dc bias path to analog ground. the value of the inductor, along with the dc blocking capacitors (c), determines the lower cutoff frequency of the composite pass-band response. an rf balun should also be considered before the rf differential gain stage and any filtering to ensure symmetrical common-mode impedance seen by the dac output while suppressing any common mode noise, harmonics, and clock spurs prior to amplification. 90? ioutp ioutn 70? l l rf diff amp c c optional balun and filter 90? lpf 09616-102 figure 99. interfacing the dac output to the self-biased differential gain stage for applications operating the AD9739A in mix mode with output frequencies extending beyond 2.2 ghz, the circuits shown in figure 100 should be considered. the circuit in figure 100 uses a wideband balun with a configuration similar to the one shown in figure 99 to provide a dc bias path for the dac outputs. the circuit in figure 101 takes advantage of ceramic chip baluns to provide a dc bias path for the dac outputs while providing excellent amplitude/phase balance over a narrower rf band. these low cost, low insertion loss baluns are available for different popular rf bands and provide excellent amplitude/ phase balance over their specified frequency range. c c mini-circuits tc1-1-462m 90? ioutp ioutn 70? l l 90? 09616-103 f igure 100. recommended mix-mode co nfiguration offering extended rf bandwidth using a tc1-1-43a+ balun murata johanson technology chip baluns 180? ioutp ioutn 70? 09616-104 fi gure 101. lowest cost and size configuration for narrow rf band operation no nideal spectral artifacts th e AD9739A output spectrum contains spectral artifacts that are not part of the original digital input waveform. these non- ideal artifacts included harmonics (including alias harmonics), images, and clock spurs. figure 102 shows a spectral plot of the AD9739A within the first nyquist zone (that is, dc to f dac /2) reconstructing a 650 mhz, 0 dbfs sine wave at 2.4 gsps. besides the desired fundamental tone at the ?7.8 dbm level, the spectrum also reveals these nonideal artifacts that also appear as spurs
AD9739A rev. 0 | page 40 of 44 above the measurement noise floor. because these nonideal artifacts are also evident in the second and third nyquist zones during mix-mode operation, the effects of these artifacts should also be considered when selecting the dac clock rate for a target rf band. 09616-105 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 200 400 600 800 1000 1200 power (dbc) frequency (mhz) hd3 hd5 hd9 hd6 hd4 fund at ?7.6dbm f dac /4 ? f out f dac /2 ? f out f dac /4 3/4 f dac /4 ? f out hd2 figure 102. spectral plot note the following important observations pertaining to these nonideal spectral artifacts: 1. a full-scale sine wave (that is, single-tone) typically represents the worst case condition because it is has a peak-to-rms ratio of 3 db and is unmodulated. harmonics and aliased harmonics of a sine wave are easy to identify because they also appear as discrete spurs. significant characterization of a high speed dac is performed using single (or multitone) signals for this reason. 2. modulated signals (that is, am, pm, or fm) do not appear as spurs but rather as signals whose power spectral density is spread over a defined bandwidth determined by the modulation parameters of the signals. any harmonics from the dac spread over a wider bandwidth determined by the order of the harmonic and bandwidth of the modulated signal. for this reason, harmonics often appear as slight bumps in the measurement noise floor and can be difficult to discern. 3. images appear as replicas of the original signal, hence, can be easier to identify. in the case of the AD9739A, internal modulation of the sampling clock at intervals related to f dac /4 generate image pairs at ? f dac , ? f dac , and ? f dac . both upper and lower sideband images associated with ? f dac fall within the first nyquist zone, while only the lower image of ? f dac and ? f dac fall back. note that the lower images appear frequency inverted. the ratio between the fundamental and various images (that is, dbc) remains mostly signal independent because the mechanism causing these images is related to corruption of the sampling clock. 4. the magnitude of these images for a given device is dependent on several factors including dac clock rate, output frequency, and mu controller phase setting. because the image magnitude is repeatable between power-up cycles (assuming the same conditions), a one-time factory calibration procedure can be used to improve suppression. calibration consists of additional dedicated dsp resources in the host that can generate a replica of the image with proper amplitude, phase, and frequency scaling to cancel the image from the dac. because the image magnitude can vary among devices, each device must be calibrated. 5. a clock spur appears at f dac /4 and integer multiples of it. similar to images, the spur magnitude is also dependent on the same factors that cause variations in image levels. however, unlike images and harmonics, clock spurs always appear as discrete spurs, albeit their magnitude shows a slight dependency on the digital waveform and output frequency. the calibration method is similar to image calibration; however, only a digital tone of equal amplitude and opposite phase at f dac /4 need be generated. 6. a large clock spur also appears at 2 f dac in either normal or mix-mode operation. this clock spur is due to the quad switch dac architecture causing switching events to occur on both edges of f dac . lab evaluation of the AD9739A figure 103 shows a recommended lab setup that was used to characterize the AD9739As performance. the dpg2 is a dual port lvds/cmos data pattern generator available from analog devices, inc., with an up to 1.25 gsps data rate. the dpg2 directly interfaces to the AD9739A evaluation board via tyco z-pack hm-zd connectors. a low phase noise/jitter rf source such as an r&s sma 100a signal generator is used for the dac clock. a +5 v power supply is used to power up the AD9739A evaluation board, and sma cabling is used to interface to the supply, clock source, and spectrum analyzer. a usb 2.0 interface to a host pc is used to communicate to both the AD9739A evaluation board and the dpg2. a high dynamic range spectrum analyzer is required to evaluate the AD9739A reconstructed waveforms ac performance. this is especially the case when measuring aclr performance for high dynamic range applications such as multicarrier docsis cmts applications. harmonic, sfdr, and imd measurements pertaining to unmodulated carriers can benefit by using a sufficiently high rf attenuation setting because these artifacts are easy to identify above the spectrum analyzer noise floor. however, reconstructed waveforms having modulated carrier(s) often benefit from the use of a high dynamic range rf amplifier and/or passive filters to measure close-in and wideband aclr performance when using spectrum analyzers of limited dynamic range.
AD9739A rev. 0 | page 41 of 44 adi pattern generator dpg2 ad9739 eval. board rhode and schwartz sma 100a agilent psa e4440a 10 mhz refin 10 mhz reout lab pc usb 2.0 gpib lvds data and dci dco 1.6ghz to 2.5ghz 3dbm power supply +5v 09616-106 figure 103. lab test setup used to characterize the AD9739A. recommended start-up sequence upon power-up of the AD9739A, a host processor is required to initialize and configure the AD9739A via its spi port. figure 104 shows a flow chart of the sequential steps required, while table 12 provides more detail on the spi register write/read operations required to implement the flow chart steps. note the following: ? a software reset is optional because the AD9739A has both an internal por circuit and a reset pin. ? the mu controller must be first enabled (and in track mode) before the data receiver controller is enabled because the dco output signal is derived from this circuitry. ? a wait period is related to f data periods. ? limit the number of attempts to lock the controllers to three; locks typically occur on the first attempt. ? hardware or software interrupts can be used to monitor the status of the controllers. configure spi port software reset set clk input cmv configure mu cont. wait a few 100s mu cont. locked? yes no yes wait a few 100s no reconfigure txdac from default setting optional configure rx data cont. rx data cont. locked? 09616-107 figure 104. flowchart for initialization and configuration of the AD9739A
AD9739A rev. 0 | page 42 of 44 table 12. recommended spi initialization step address (hex) write value comments 1 0x00 0x00 configure for the 4-wire spi mode with msb. note that bits[7:5] must be mirrored onto bits[2:0] because the msb/lsb format can be unknown at power-up. 2 0x00 0x20 software reset to default spi values. 3 0x00 0x00 clear the reset bit. 4 0x22 0x0f 5 0x23 0x0f set the common-mode voltage of dacclk_p and dacclk_n inputs 6 0x24 0x30 7 0x25 0x80 8 0x27 0x44 9 0x28 0x6c 10 0x29 0xcb 11 0x26 0x02 configure the mu controller. 12 0x26 0x03 enable the mu controller search and track mode. 13 wait for 160 k 1/f data cycles. 14 0x2a read back register 0x2a and confirm that it is equal to 0x01 to ensure that the dll loop is locked. if it is not locked, proceed to step 10 and repeat. limit attempts to three before breaking out of the loop an d reporting a mu lock failure. 15 ensure that the AD9739A is fed with dci clock input from the data source. 16 0x13 0x72 set fine_del_skew to 2. 17 0x10 0x00 disable the data rx controller before enabling it. 18 0x10 0x02 enable the data rx controller for loop and irq. 19 0x10 0x03 enable the data rx cont roller for search and track mode. 20 wait for 135 k 1/f data cycles. 21 0x21 read back register 0x21 and confirm that it is equal to 0x09 to ensure that the dll loop is locked and tracking. if it is not locked and tracking, proceed to step 16 and repeat. limit attempts to three before breaking out of the loop and reporting an rx data lock failure. 22 0x06 0x07 0x00 0x02 optional: modify the txdac i outfs setting (the default is 20 ma). 23 0x08 0x00 optional: modify the txdac operati on mode (the defaul t is normal mode).
AD9739A rev. 0 | page 43 of 44 outline dimensions 12.10 12.00 sq 11.90 seating plane 0.43 max 0.25 min detail a 0.55 0.50 0.45 0.12 max coplanarity 1.00 max 0.85 min ball diameter 0.80 bsc 0.80 ref 10.40 bsc sq a b c d e f g h j k l m n p 14 13 12 11 10 8 7 6 3 2 1 95 4 a 1 corne r index area top view ball a1 indicator detail a bottom view 1.40 max compliant to jedec standards mo-205-ae. 012006-0 figure 105. 160-ball chip scale package ball grid array [csp_bga] (bc-160-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9739Abbcz ?40c to +85c 160-ball chip scale package ball grid array [csp_bga] bc-160-1 AD9739Abbczrl ?40c to +85c 160- ball chip scale package ball grid array [csp_bga] bc-160-1 AD9739A-ebz evaluation board 1 z = rohs compliant part.
AD9739A rev. 0 | page 44 of 44 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09616-0-1/11(0)

▲Up To Search▲

Price & Availability of AD9739A

	To Download AD9739A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .